Datasheet > EMF04P02H

EMF04P02H

更新时间： 2024-11-21 17:15:39

品牌	Logo	应用领域
杰力科技 - EXCELLIANCE		/
页数	文件大小	规格书
6页	231K
描述
EDFN5X6

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中文翻译

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数据手册

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EMF04P02H 数据手册

EMF04P02H

P‐Channel Logic Level Enhancement Mode Field Effect Transistor

Product Summary:

BV^DSS

‐20V

5.5mΩ

‐72A

DSON (MAX.)

UIS, Rg 100% Tested

Pb‐Free Lead Plating & Halogen Free

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

±12

‐72

UNIT

Gate‐Source Voltage

V_GS

T_C= 25 °C

Continuous Drain Current

I_D

T_C= 100 °C

‐45

Pulsed Drain Current¹

I_DM

I_AS

‐240

‐48

Avalanche Current

L = 0.1mH, I_AS=‐48A, R

L = 0.05mH

G=25Ω

Avalanche Energy

E_AS

E_AR

115

Repetitive Avalanche Energy²

T_C= 25 °C

Power Dissipation

P_D

°C

T_C= 100 °C

Operating Junction & Storage Temperature Range

T_j, T_stg

‐55 to 150

100% UIS testing in condition of V_D=‐15V, L=0.1mH, V_G=‐5V, I_L=‐30A, Rated V_DS=‐20V P‐CH

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

R_JC

TYPICAL

MAXIMUM

UNIT

Junction‐to‐Case

Junction‐to‐Ambient³

2.5

°C / W

62.5

R_JA

¹Pulse width limited by maximum junction temperature.

²Duty cycle  1％

2016/10/3ꢀ

p.1ꢀ

12 3 4 5 6

中文翻译

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