Datasheet > EMF04P02V

EMF04P02V

更新时间： 2024-11-21 17:15:27

品牌	Logo	应用领域
杰力科技 - EXCELLIANCE		/
页数	文件大小	规格书
7页	867K
描述
EDFN3X3

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中文翻译

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数据手册

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EMF04P02V 数据手册

EMF04P02V

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Product Summary:

BVDSS

-20V

6.3mΩ

-46A

RDSON (MAX.)

P-Channel MOSFET

UIS, Rg 100% Tested

Pb-Free Lead Plating & Halogen Free

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

±12

UNIT

Gate-Source Voltage

V_GS

T_C= 25 °C

-46

Continuous Drain Current

I_D

T_A= 25 °C

-16

-29

-180

-48

115

T_C= 100 °C

Pulsed Drain Current¹

I_DM

I_AS

Avalanche Current

L = 0.1mH, I_AS=-48A, RG=25Ω

L = 0.05mH

Avalanche Energy

E_AS

E_AR

Repetitive Avalanche Energy²

T_C= 25 °C

Power Dissipation

P_D

T_C= 100 °C

8.3

2.5

T_A= 25 °C

P_D

°C

T_A= 100 °C

Operating Junction & Storage Temperature Range

T_j, T_stg

-55 to 150

100% UIS testing in condition of V_D=-15V, L=0.1mH, V_G=-5V, I_L=-20A, Rated V_DS=-20V P-CH

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

R_JC

TYPICAL

MAXIMUM

UNIT

Junction-to-Case

Junction-to-Ambient³

°C / W

R_JA

¹Pulse width limited by maximum junction temperature.

²Duty cycle  1％

2019/6/25

p.1

12 3 4 5 6 7

中文翻译

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