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EM6AA320BI-6MS/6MSG PDF预览

EM6AA320BI-6MS/6MSG

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
钰创 - ETRON 动态存储器双倍数据速率
页数 文件大小 规格书
16页 365K
描述
8M x 32 DDR SDRAM

EM6AA320BI-6MS/6MSG 数据手册

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EtronTech  
EM6AA320-XXMS  
8Mx32 DDR SDRAM  
VSS  
Supply  
.
Ground:  
for the input buffers and core logic  
Ground  
VDDQ  
VSSQ  
VREF  
NC  
Supply  
Supply  
Supply  
-
DQ Power:  
Provide isolated power to DQs for improved noise immunity.  
DQ Ground:  
Provide isolated ground to DQs for improved noise immunity.  
Reference Voltage for Inputs:  
+0.5 x VDDQ  
No Connect:  
These pins should be left unconnected.  
Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any  
applications using the single ended clocking, apply VREF to CK# pin.  
Operation Mode  
Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2  
shows the truth table for the operation commands.  
Table 2. Truth Table (Note (1), (2) )  
Command  
BankActivate  
BankPrecharge  
PrechargeAll  
Write  
State  
Idle(3)  
Any  
CKEn-1 CKEn DM BA1 BA0 A8 A11-A9, A7-0 CS# RAS# CAS# WE#  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
V
V
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
L
V
V
X
V
V
V
V
L
Row Address  
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
H
L
X
X
L
L
L
H
H
H
H
L
H
H
H
L
H
L
L
L
H
L
X
X
Any  
Active(3)  
Active(3)  
Active(3)  
L
Column  
Address  
A0~A7, A9  
H
L
H
L
L
Write and AutoPrecharge  
Read  
Read and Autoprecharge Active(3)  
Mode Register Set  
Extended Mode Register Set  
No-Operation  
Device Deselect  
Burst Stop  
L
L
L
H
H
L
Idle  
Idle  
OP code  
L
H
X
X
X
X
X
L
L
L
Any  
Any  
Active(4)  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
L
H
X
H
L
H
X
L
AutoRefresh  
SelfRefresh Entry  
Idle  
Idle  
Idle  
H
H
X
H
X
H
X
H
X
X
L
L
X
H
X
H
X
H
X
X
X
H
X
H
X
H
X
X
SelfRefresh Exit  
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(Self Refresh)  
Power Down Mode Entry Idle/Active(5)  
Any  
Power Down Mode Exit  
(Power Down)  
H
Active  
Active  
H
H
X
X
L
X
X
X
X
X
X
X
X
Data Write/Output Enable  
Data Mask/Output Disable  
H
Note:  
1. V = Valid data, X = Don't Care, L = Low level, H = High level  
2. CKEn signal is input level when commands are provided.  
CKEn-1 signal is input level one clock cycle before the commands are provided.  
3. These are states of bank designated by BA0, BA1signals.  
4. Read burst stop with BST command for all burst types.  
5. Power Down Mode can not enter in the burst operation.  
When this command is asserted in the burst cycle, device state is clock suspend mode.  
5
Rev 0.7  
May. 2006  

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