Datasheet > EM6AA320-XXMS

EM6AA320-XXMS

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
钰创 - ETRON		动态存储器双倍数据速率
页数	文件大小	规格书
16页	365K
描述
8M x 32 DDR SDRAM

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EM6AA320-XXMS 数据手册

EtronTech

EM6AA320-XXMS

8M x 32 DDR SDRAM

(Rev 0.7 May/2006)

Features

Overview

Fast clock rate: 300/275/250/200/166 MHz

Differential Clock CK & CK# input

•

The EM6AA320 DDR SDRAM is a high-speed CMOS

double data rate synchronous DRAM containing 256

Mbits. It is internally configured as a quad 2M x 32

DRAM with a synchronous interface (all signals are

registered on the positive edge of the clock signal, CK).

4 Bi-directional DQS. Data transactions on both

edges of DQS (1DQS / Byte)

DLL aligns DQ and DQS transitions

Edge aligned data & DQS output

Center aligned data & DQS input

4 banks operation

•

Data outputs occur at both rising edges of CK and CK#.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence.

Programmable mode and extended mode

registers

Accesses begin with the registration of a BankActivate

command, which is then followed by a Read or Write

command.

- CAS# Latency: 3, 4

- Burst length: 2, 4, 8

The EM6AA320 provides programmable Read or Write

burst lengths of 2, 4, 8. An auto precharge function may

be enabled to provide a self-timed row precharge that is

initiated at the end of the burst sequence.

- Burst Type: Sequential & Interleave

Full page burst length for sequential type only

Start address of full page burst should be even

•

The refresh functions, either Auto or Self Refresh are

easy to use.

All inputs except DQ’s & DM are at the positive

edge of the system clock

In addition, EM6AA320 features programmable DLL

option. By having a programmable mode register and

extended mode register, the system can choose the

most suitable modes to maximize its performance.

No Write-Interrupted by Read function

4 individual DM control for write masking only

Auto Refresh and Self Refresh

4096 refresh cycles / 32ms

•

These devices are well suited for applications requiring

high memory bandwidth, result in a device particularly

well suited to high performance main memory and

graphics applications.

Power supplies :

_DD= 2.5V ± 5%

_DDQ= 2.5V ± 5%

Interface : SSTL_2 I/O compatible

Standard 144-ball FBGA package

Pb-free package is available

•

Ordering Information

Part Number

Frequency Power Supply

Package

FBGA

EM6AA320BI-3.3MS^(*)

EM6AA320BI-3.6MS^(*)

EM6AA320BI-4MS/4MSG^(*)

EM6AA320BI-5MS/5MSG^(*)

EM6AA320BI-6MS/6MSG^(*)

300MHz

275MHz

250MHz

200MHz

166MHz

V_DD2.5V

_DDQ2.5V

Note (*) : S indicates stacked die package

G indicates Pb-free package

12 3 4 5 6 7...16

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