EtronTech
EM6AA320-XXMS
8Mx32 DDR SDRAM
Pin Descriptions
Table 1. Pin Details of EM6AA320
Description
Symbol
Type
CK, CK#
Input
Differential Clock:
CK, CK# are driven by the system clock. All SDRAM input
commands are sampled on the positive edge of CK. Both CK and CK# increment the
internal burst counter and controls the output registers.
CKE
Input
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
BA0, BA1
A0-A11
Input
Input
Bank Select:
BA0 and BA1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. They also define which Mode Register or
Extended Mode Register is loaded during a Mode Register Set command.
Address Inputs:
A0-A11 are sampled during the Bank Activate command (row
address A0-A11) and Read/Write command (column address A0-A7, and A9 with A8
defining Auto Precharge) to select one location out of the memory array in the
respective bank. During a Precharge command, A8 is sampled to determine if all
banks are to be precharged (A8 = HIGH). The address inputs also provide the op-
code during a Mode Register Set or Extended Mode Register Set command.
CS#
Input
Input
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
RAS#
Row Address Strobe:
The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH" either
the BankActivate command or the Precharge command is selected by the WE#
signal. When the WE# is asserted "HIGH," the BankActivate command is selected
and the bank designated by BS is turned on to the active state. When the WE# is
asserted "LOW," the Precharge command is selected and the bank designated by BS
is switched to the idle state after the precharge operation.
CAS#
WE#
Input
Input
Column Address Strobe:
The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CK. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is
started by asserting CAS# "LOW" Then, the Read or Write command is selected by
asserting WE# "HIGH " or “LOW".
Write Enable:
The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
DQS0-DQS3 Input /
Output
Bidirectional Data Strobe:
bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to
DQ24-DQ31.
The DQSx signals are mapped to the following data
DM0 - DM3
Input
Data Input Mask:
DM0-DM3 are byte specific. Input data is masked when DM is
sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-
DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.
DQ0 - DQ31 Input /
Output
Data I/O:
The DQ0-DQ31 input and output data are synchronized with the positive
edges of CK and CK#. The I/Os are byte-maskable during Writes.
VDD
Supply
Power Supply: Power for the input buffers and core logic.
4
Rev 0.7
May. 2006
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