Datasheet > EM6A9320BIB-4IH

EM6A9320BIB-4IH

更新时间： 2022-02-26 13:08:28

品牌	Logo	应用领域
钰创 - ETRON		动态存储器双倍数据速率
页数	文件大小	规格书
61页	502K
描述
4M x 32 bit DDR Synchronous DRAM (SDRAM)

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EM6A9320BIB-4IH 数据手册

EM6A9320BIB

EtronTech

Mode Register Set (MRS)

The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs

CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The

default value of the Mode Register is not defined; therefore the Mode Register must be written by the user.

Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by

asserting Low on

, BA1 and BA0 (the device should have all banks idle with no bursts in

CS RAS CAS WE

progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A11 and

BA0, BA1 in the same cycle in which and are asserted Low is written into the Mode

CS RAS CAS

A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should

be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be

used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific

codes for various burst lengths, burst types and CAS latencies.

Table 5. Mode Register Bitmap

BA1 BA0 A11 A10 A9

A0 Address Field

T.M.

CAS Latency

Burst Length

Mode Register

A8 A7

Test Mode

Normal mode

DLL Reset

A6 A5 A4 CAS Latency A3 Burst Type A2 A1 A0 Burst Length

Reserved

0 Sequential

Interleave

Test mode

Reserved

2.5

Reserved

BA0 Mode

MRS

EMRS

Reserved

Burst Length Field (A2~A0)

•

This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be

2, 4, and 8.

Table 6. Burst Length

Burst Length

Reserved

Etron Confidential

Rev 1.0

July /2012

1...4 5 678 9 10...61

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