EM6A9320BIB
EtronTech
Pin Descriptions
Table 3. Pin Details of EM6A9320
Symbol
CK,
Type
Description
Input
CK
Differential Clock: CK,
are driven by the system clock. All SDRAM input
CK
commands are sampled on the positive edge of CK. Both CK and
internal burst counter and controls the output registers.
increment the
CK
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
BA0, BA1
A0-A11
Input
Input
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. They also define which Mode Register or
Extended Mode Register is loaded during a Mode Register Set command.
Address Inputs: A0-A11 are sampled during the Bank Activate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A8 defining
Auto Precharge) to select one location out of the 1M available in the respective bank.
During a Precharge command, A8 is sampled to determine if all banks are to be
precharged (A8 = HIGH). The address inputs also provide the op-code during a Mode
Register Set or Extended Mode Register Set command.
Input
Input
Chip Select:
enables (sampled LOW) and disables (sampled HIGH) the
CS
CS
command decoder. All commands are masked when
is sampled HIGH.
CS
CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The
signal defines the operation commands in
RAS
RAS
conjunction with the
and /WE signals and is latched at the positive edges of CK.
CAS
are asserted "LOW" and
When
and
is asserted "HIGH" either the
CAS
RAS
CS
BankActivate command or the Precharge command is selected by the
signal.
WE
is asserted "HIGH," the BankActivate command is selected and the
When the
WE
bank designated by BA is turned on to the active state. When the
is asserted
WE
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
Input
Input
Column Address Strobe: The
signal defines the operation commands in
CAS
WE
CAS
conjunction with the
and /WE signals and is latched at the positive edges of CK.
RAS
When /RAS is held "HIGH" and
is asserted "LOW" the column access is started
CS
by asserting
"LOW" Then, the Read or Write command is selected by asserting
CAS
"HIGH " or “LOW".
WE
Write Enable: The
signal defines the operation commands in conjunction with
WE
signals and is latched at the positive edges of CK. The
the
and
input
WE
RAS
CAS
is used to select the BankActivate or Precharge command and Read or Write
command.
DQS0-DQS3 Input /
Output
Bidirectional Data Strobe: The DQSx signals are mapped to the following data
bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, and DQS3 to
DQ24-DQ31.
DM0 - DM3
Input
Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is
sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-
DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.
DQ0 - DQ31 Input /
Output
Data I/O: The DQ0-DQ31 input and output data are synchronized with positive and
negative edges of DQS0~DQS3. The I/Os are byte-maskable during Writes.
Power Supply: Power for the input buffers and core logic.
VDD
VSS
Supply
Supply
.
Ground: Ground for the input buffers and core logic
Etron Confidential
4
Rev 1.0
July /2012
5秒后页面跳转
VIPER22A的资料手册解读、引脚参数说明、代换型号推荐
ADS1256的资料手册解读、采集电压范围、读数变化原因分析及实际测量遇到的问题
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
