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EH1445SJTTS-9.834MTR PDF预览

EH1445SJTTS-9.834MTR

更新时间: 2024-11-12 05:44:03
品牌 Logo 应用领域
日蚀 - ECLIPTEK 输出元件
页数 文件大小 规格书
10页 936K
描述
CRYSTAL OSCILLATOR, CLOCK, CMOS/TTL OUTPUT

EH1445SJTTS-9.834MTR 数据手册

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Ecliptek | EH14 Series Oscillator  
http://www.ecliptek.com/oscillators/EH14/  
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EH14 Series Oscillator  
Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc J-Lead 9.8mm x 14.0mm Plastic Surface Mount (SMD)  
2011/65 +  
168 SVHC  
2015/863  
Revision F 08/14/2012  
ectrical Specifications  
Nominal Frequency  
1.000MHz to 155.520MHz  
Some frequencies within this range may not be available.  
requency  
(Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the  
olerance/Stability  
Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year  
Aging at 25°C, Shock, and Vibration)  
±100ppm Maximum  
±50ppm Maximum  
±25ppm Maximum  
±20ppm Maximum  
Operating Temperature  
ange  
0°C to +70°C  
-40°C to +85°C  
upply Voltage (V  
nput Current  
)
DD  
5.0V  
±10%  
DC  
No Load  
50mA Maximum  
Output Voltage Logic  
High (V  
2.4V  
0.4V  
Minimum with TTL Load, V -0.4V  
DD  
Minimum with HCMOS Load, IOH = -16mA  
DC  
DC  
DC  
)
OH  
Output Voltage Logic  
ow (V  
Maximum with TTL Load, 0.5V  
Maximum with HCMOS Load, IOL = +16mA  
DC  
)
OL  
Duty Cycle  
50 ±10(%)(Measured at 1.4V  
with TTL Load or 50% of waveform with HCMOS Load  
DC  
over Nominal Frequency of 1MHz to 70MHz; Measured at 50% of waveform over Nominal  
Frequency of 70.000001MHz to 155.52MHz)  
50 ±5(%) (Measured at 50% of waveform with TTL Load or with HCMOS Load)  
ise Time/Fall Time  
oad Drive Capability  
Measured at 0.8V  
to 2.0V  
with TTL Load; Measured at 20% to 80% of waveform  
DC  
DC  
with HCMOS Load  
6nSec Maximum over Nominal Frequency of 1MHz to 70MHz  
4nSec Maximum over Nominal Frequency of 70.000001MHz to 155.52MHz  
10TTL Load or 50pF HCMOS Load Maximum over Nominal Frequency of 1MHz to 70MHz  
5TTL Load or 15pF HCMOS Load Maximum over Nominal Frequency of 70.000001MHz to  
155.52MHz  
Output Logic Type  
in 1 Connection  
CMOS  
TTL  
Tri-State (Disabled Output: High Impedance)  
ri-State Input Voltage  
Vih and Vil)  
+2.2V  
Minimum to enable output, +0.8V Maximum to disable output (High  
DC  
DC  
Impedance), No Connect to enable output.  
±250pSec Maximum, ±100pSec Typical  
±50pSec Maximum, ±30pSec Typical  
bsolute Clock Jitter  
One Sigma Clock Period  
itter  
ging (at 25°C)  
±5ppm/year Maximum  
1 of 10  
28-Jan-2016 1:02 PM  

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