Datasheet > EDI8F8257LP70B6I

EDI8F8257LP70B6I

更新时间： 2023-01-03 08:25:39

品牌	Logo	应用领域
WEDC		静态存储器
页数	文件大小	规格书
6页	142K
描述
SRAM Module, 256KX8, 70ns, CMOS, DIP-32

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EDI8F8257LP70B6I 数据手册

EDI8F8257C

256Kx8 Static RAM CMOS, Module

DESCRIPTION

FEATURES

256Kx8 bit CMOS Static

The EDI8F8257C is a 2Mb CMOS Static RAM based on two

128Kx8 Static RAMs mounted on a multi-layered epoxy laminate

(FR4) substrate.

Random Access Memory

Access Times 70, 85 and 100ns

Data Retention Function (LP version)

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

Functional equivalence to the monolithic 2Mb Static RAM is

achieved by utilization of an on-board decoder that interprets the

higher order address (A17) to select one of the 128Kx8 Static

RAMs.

The 32 pin DIP pinout adheres to the JEDEC standard for the two

megabit device, to ensure compatibility with future monolithics.

High Density Packaging

32 Pin SOIC Module, No. 21 (OBSOLETE)

32 Pin DIP Module, No. 184

Single +5V (±10%) Supply Operation

The device is available with Low Power and Data Retention

(EDI8F8257LP).

All inputs and outputs are TTL compatible and operate from a

single 5V supply. Fully asynchronous, the EDI8F8257C requires

no clocks or refreshing for operation.

PIN CONFIGURATIONS AND BLOCK DIAGRAM

PIN NAMES

AØ-A17

Address Inputs

Chip Enable

Write Enable

Output Enable

DQØ-DQ7

VCC

VSS

Common Data Input/Output

Power (+5V±10%)

Ground

No Connection

Sept. 2001 Rev. 9

ECO #14605

White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com

12 3 4 5 6

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