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EDI88512LPA17KI PDF预览

EDI88512LPA17KI

更新时间： 2024-11-06 21:13:15
品牌 Logo 应用领域
WEDC 静态存储器内存集成电路
页数 文件大小 规格书
9页 158K
描述
Standard SRAM, 512KX8, 17ns, CMOS, CDSO36, CERAMIC, LCC-36

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EDI88512LPA17KI 数据手册

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EDI88512CA  
White Electronic Designs  
512Kx8 Monolithic SRAM, SMD 5962-95600  
FEATURES  
The EDI88512CA is a 4 megabit Monolithic CMOS  
Static RAM.  
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„
„
„
„
„
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Access Times of 15, 17, 20, 25, 35, 45, 55ns  
Data Retention Function (LPA version)  
TTL Compatible Inputs and Outputs  
Fully Static, No Clocks  
The 32 pin DIPpinout adheres to the JEDEC evolutionary  
standard for the four megabit device.All 32 pin packages  
are pin for pin upgrades for the single chip enable 128K  
x 8, the EDI88128CS. Pins 1 and 30 become the higher  
order addresses.  
Organized as 512Kx8  
The 36 pin revolutionary pinout also adheres to the  
JEDEC standard for the four megabit device. The center  
pin power and ground pins help to reduce noise in high  
performance systems. The 36 pin pinout also allows the  
user an upgrade path to the future 2Mx8.  
Commercial, Industrial and Military Temperature Ranges  
32 lead JEDEC Approved Evolutionary Pinout  
• Ceramic Sidebrazed 600 mil DIP (Package 9)  
• Ceramic Sidebrazed 400 mil DIP (Package 326)  
• Ceramic 32 pin Flatpack (Package 344)  
• Ceramic Thin Flatpack (Package 321)  
• Ceramic SOJ (Package 140)  
ALow Power version with Data Retention (EDI88512LPA)  
is also available for battery backed applications. Military  
product is available compliant to Appendix A of MIL-  
PRF-38535.  
„
„
36 lead JEDEC Approved Revolutionary Pinout  
• Ceramic Flatpack (Package 316)  
• Ceramic SOJ (Package 327)  
*This product is subject to change without notice.  
• Ceramic LCC (Package 502)  
Single +5V (±10%) Supply Operation  
FIG. 1  
PIN CONFIGURATION  
PIN DESCRIPTION  
I/O0-7  
Data Inputs/Outputs  
Address Inputs  
Write Enables  
Chip Selects  
36 PIN  
TOP VIEW  
32 PIN  
TOP VIEW  
A0-18  
WE#  
CS#  
OE#  
VCC  
1
2
36 NC  
35 A18  
34 A17  
33 A16  
32 A15  
31 OE#  
30 I/O7  
29 I/O6  
A0  
A1  
32 Vcc  
31 A15  
30 A17  
29 WE#  
28 A13  
27 A8  
A18  
A16  
A14  
A12  
A7  
1
2
Output Enable  
Power (+5V ±10%)  
Ground  
3
4
A2  
A3  
3
4
5
A4  
VSS  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
CS#  
I/O0  
I/O1  
Vcc  
Vss  
I/O2  
I/O3  
WE#  
A5  
A6  
A7  
A8  
A9  
A6  
6
NC  
Not Connected  
26 A9  
A5  
7
32 pin  
Evolutionary  
36 pin  
Revolutionary  
25 A11  
24 OE#  
23 A10  
22 CS#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
8
Vss  
Vcc  
27  
A4  
28  
9
A3  
BLOCK DIAGRAM  
I/O5  
26  
10  
11  
12  
13  
14  
A2  
I/O4  
A14  
A13  
A12  
25  
24  
23  
22  
A1  
Memory Array  
A0  
I/O0  
I/O1  
21 A11  
20 A10  
NC  
I/O2 15  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
0-18  
I/O0-7  
Vss  
16  
19  
WE#  
CS#  
OE#  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
October 2006  
Rev. 12  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
1234567...9

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EDI88512LPA17MBG MICROSEMI

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EDI88512LPA17MBG WEDC

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EDI88512LPA-17MBG MICROSEMI

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EDI88512LPA17MBRP WEDC

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EDI88512LPA17MCG WEDC

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 		Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, ROHS COMPLIANT, PLASTIC, SOJ-36
EDI88512LPA-17MCG MICROSEMI

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 		Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, ROHS COMPLIANT, PLASTIC, SOJ-36
EDI88512LPA17MCRP WEDC

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EDI88512LPA17MI ETC

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 		x8 SRAM
EDI88512LPA17MIG WEDC

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