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EDI88512C/LP-C PDF预览

EDI88512C/LP-C

更新时间: 2024-11-01 23:50:07
品牌 Logo 应用领域
其他 - ETC 电池静态存储器
页数 文件大小 规格书
7页 124K
描述
SRAM

EDI88512C/LP-C 数据手册

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EDI88512C  
HI-RELIABILITY PRODUCT  
512Kx8 Monolithic SRAM CMOS  
FEATURES  
512Kx8 bit CMOS Static  
The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.  
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard  
for the four megabit device. Both the DIP and CSOJ packages are  
pin for pin upgrades for the single chip enable 128K x 8, the  
EDI88128C. Pins 1 and 30 become the higher order addresses.  
Random Access Memory  
• Access Times of 70, 85, 100ns  
• Data Retention Function (LP version)  
• TTL Compatible Inputs and Outputs  
• Fully Static, No Clocks  
A Low Power version with Data Retention (EDI88512LP) is also  
available for battery backed applications. Military product is  
available compliant to Appendix A of MIL-PRF-38535.  
32 lead JEDEC Approved Evolutionary Pinout  
• Ceramic Sidebrazed 600 mil DIP (Package 9)  
• Ceramic SOJ (Package 140)  
Single +5V (±10%) Supply Operation  
FIG. 1 PIN CONFIGURATION  
PIN DESCRIPTION  
I/O0-7  
A0-18  
WE  
CS  
Data Inputs/Outputs  
Address Inputs  
Write Enables  
Chip Selects  
TOP VIEW  
A18  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2 10  
A1 11  
AØ 12  
I/OØ 13  
I/O1 14  
I/O2 15  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 A17  
29 WE  
28 A13  
27 A8  
OE  
Output Enable  
Power (+5V ±10%)  
Ground  
VCC  
VSS  
NC  
26 A9  
25 A11  
24 OE  
23 A10  
22 CS  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
Not Connected  
BLOCK DIAGRAM  
Memory Array  
VSS 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
Ø-18  
I/OØ-7  
WE  
CS  
OE  
1
February 2001 Rev. 11  
White Electronic Designs Corporation • www.whiteedc.com • (602) 437-1520  

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