EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
■ Access Times of 15, 17, 20, 25, 35, 45, 55ns
■ Data Retention Function (LPA version)
■ TTL Compatible Inputs and Outputs
■ Fully Static, No Clocks
The 32 pin DIP pinout adheres to the JEDEC evolu-
tionary standard for the four megabit device. All 32 pin
packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128CS. Pins 1 and 30 be-
come the higher order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The cen-
ter pin power and ground pins help to reduce noise in
high performance systems. The 36 pin pinout also
allows the user an upgrade path to the future 2Mx8.
■ Organized as 512Kx8
■ Commercial, Industrial and Military Temperature Ranges
■ 32 lead JEDEC Approved Evolutionary Pinout
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Ceramic Sidebrazed 600 mil DIP (Package 9)
Ceramic Sidebrazed 400 mil DIP (Package 326)
Ceramic 32 pin Flatpack (Package 344)
Ceramic Thin Flatpack (Package 321)
Ceramic SOJ (Package 140)
A
Low Power version with Data Retention
(EDI88512LPA) is also available for battery backed
applications. Military product is available compliant to
Appendix A of MIL-PRF-38535.
■ 36 lead JEDEC Approved Revolutionary Pinout
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Ceramic Flatpack (Package 316)
Ceramic SOJ (Package 327)
Ceramic LCC (Package 502)
■ Single +5V (±10%) Supply Operation
FIG. 1 PIN CONFIGURATION
PIN DESCRIPTION
I/O0-7 Data Inputs/Outputs
36 PIN
32 PIN
TOP VIEW
TOP VIEW
A0-18
WE
CS
Address Inputs
Write Enables
Chip Selects
A18
A16
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
32 VCC
31 A15
30 A17
29 WE
28 A13
27 A8
OE
Output Enable
Power (+5V ±10%)
Ground
VCC
VSS
NC
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Not Connected
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
BLOCK DIAGRAM
Memory Array
VSS 16
Address
Buffer
Address
Decoder
I/O
Circuits
A
-18
I/O -7
WE
CS
OE
Aug. 2002 Rev. 9
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com