Datasheet > EDI88130C/LP-N

EDI88130C/LP-N

更新时间： 2024-11-01 23:50:07

品牌	Logo	应用领域
其他 - ETC		电池静态存储器
页数	文件大小	规格书
8页	156K
描述
SRAM

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中文翻译

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数据手册

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EDI88130C/LP-N 数据手册

EDI88128C

HI-RELIABILITY PRODUCT

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

The EDI88128C is a high speed, high performance, Monolithic

CMOS Static RAM organized as 128Kx8.

■ Access Times of 70, 85, 100ns

■ Available with Single Chip Selects (EDI88128) or Dual Chip

The device is also available as EDI88130C with an additional chip

select line (CS2) which will automatically power down the device

when proper logic levels are applied.

Selects (EDI88130)

■ 2V Data Retention (LP Versions)

■ CS and OE Functions for Bus Control

■ TTL Compatible Inputs and Outputs

■ Fully Static, No Clocks

The second chip select line (CS2) can be used to provide system

memory security during power down in non-battery backed up

systems and simplifiy decoding schemes in memory banking

where large multiple pages of memory are required.

■ Organized as 128Kx8

The EDI88128C and the EDI88130C have eight bi-directional in-

put-output lines to provide simultaneous access to all bits in a

word. An automatic power down feature permits the on-chip

circuitry to enter a very low standby mode and be brought back

into operation at a speed equal to the address access time.

■ Industrial, Military and Commercial Temperature Ranges

■ Thru-hole and Surface Mount Packages JEDEC Pinout

• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)

• 32 lead Ceramic ZIP (Package 100)

• 32 lead Ceramic SOJ (Package 140)

Low power versions, EDI88128LP and EDI88130LP, offer a 2V data

retention function for battery back-up opperation. Military prod-

uct is available compliant to Appendix A of MIL-PRF-38535.

■ Single +5V (±10%) Supply Operation

FIG. 1 PIN CONFIGURATION

PIN DESCRIPTION

32 DIP

I/O0-7

A0-16

Data Inputs/Outputs

Address Inputs

Write Enable

32 SOJ

32 ZIP

TOP VIEW

A16

A14

A12

A6 11

A5 13

A4 15

A3 17

A2 19

A1 21

AØ 23

I/OØ 25

I/O1 27

I/O2 29

A16

A14

A12

A2 10

A1 11

AØ 12

I/OØ 13

I/O1 14

I/O2 15

32 VCC

VCC

A15

NC/CS2*

CS1, CS2

Chip Selects

31 A15

30 NC/CS2*

29 WE

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CS1

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

Output Enable

Power (+5V ±10%)

Ground

VCC

10 A13

12 A8

14 A9

VSS

Not Connected

16 A11

18 OE

20 A10

22 CS1

24 I/O7

26 I/O6

28 I/O5

30 I/O4

32 I/O3

BLOCK DIAGRAM

Memory Array

VSS 31

SS 16

Address

Buffer

Address

Decoder

I/O

Circuits

Ø-16

I/OØ-7

CS1

* Pin 30 is NC for 88128 or CS2 for 88130.

July 1999 Rev. 13

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

12 3 4 5 6 7 8

中文翻译

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与EDI88130C/LP-N相关器件

型号	品牌	获取价格	描述	数据表
EDI88130C100CB	ETC	获取价格	128KX8 MONOLITHIC SRAM, SMD 5962-89598
EDI88130C100CC	ETC	获取价格	128KX8 MONOLITHIC SRAM, SMD 5962-89598
EDI88130C100CI	ETC	获取价格	128KX8 MONOLITHIC SRAM, SMD 5962-89598
EDI88130C100CM	ETC	获取价格	128KX8 MONOLITHIC SRAM, SMD 5962-89598
EDI88130C100NB	WEDC	获取价格	Standard SRAM, 128KX8, 100ns, CMOS, CDSO32,
EDI88130C100NC	ETC	获取价格	128KX8 MONOLITHIC SRAM, SMD 5962-89598
EDI88130C100NI	ETC	获取价格	128KX8 MONOLITHIC SRAM, SMD 5962-89598
EDI88130C100NM	ETC	获取价格	128KX8 MONOLITHIC SRAM, SMD 5962-89598
EDI88130C100ZB	ETC	获取价格	x8 SRAM
EDI88130C100ZC	ETC	获取价格	x8 SRAM

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