The EDI88128C is a high speed, high performance, Mono-
lithic CMOS Static RAM organized as 128Kx8.
n Access Times of 70, 85, 100ns
n Available with Single Chip Selects (EDI88128) or Dual
Chip Selects (EDI88130)
n 2V Data Retention (LP Versions)
n CS and OE Functions for Bus Control
n TTL Compatible Inputs and Outputs
n Fully Static, No Clocks
The device is also available as EDI88130C with an additional
chip select line (CS2) which will automatically power down
the device when proper logic levels are applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in memory
banking where large multiple pages of memory are required.
n Organized as 128Kx8
n Industrial, Military and Commercial Temperature Ranges
n Thru-hole and Surface Mount Packages JEDEC Pinout
•32 pin Ceramic DIP, 0.6 mils wide (Package 9)
•32 lead Ceramic SOJ (Package 140)
n Single +5V ( 10ꢀ) Supply Operation
The EDI88128C and the EDI88130C have eight bi-directional
input-output lines to provide simultaneous access to all
bits in a word. An automatic power down feature permits
the on-chip circuitry to enter a very low standby mode and
be brought back into operation at a speed equal to the
address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a
2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
FIG. 1
32 DIP
32 SOJ
I/O0-7
A0-16
WE
DataInputs/Outputs
AddressInputs
Write Enable
CS1, CS2
OE
Chip Selects
NC
A16
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
32 VCC
Output Enable
Power (+5V 10ꢀ)
Ground
31 A15
30 NC/CS2*
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
VCC
VSS
NC
Not Connected
A2 10
A1 11
AØ 12
I/OØ 13
I/O1 14
I/O2 15
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
VSS 16
* Pin 30 is NC for 88128 or CS2 for 88130.
March 2002 Rev. 16
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com