Freescale Semiconductor, Inc.
HYBRID MCU/DSP
56853
120 MIPS Hybrid Processor
TARGET APPLICATIONS
BENEFITS
• DTAD
• Easy to program with flexible
application development tools
• Flexible 6-Channel Direct Memory
Access (DMA) allows both internal and
external memory transfers with almost
no CPU interruption
• Feature phone
• Voice recognition and command
• Embedded modem/data pump
• Voice processing
• Supports multiple processor
connections
• Serial peripheral interface with master
and slave mode supporting connection
to other processors or serial memory
devices
• Low bit rate audio processing
• Multi-processor Telephony
Systems
• LCD and keypad support
• General purpose devices
• Automotive hands-free
• 16-bit quad timer module (with four
external pins) that allows
capture/compare functionality, and can
be cascaded
• External memory expansion up to 2M
words program memory or up to 8M
words data memory increases
capabilities of device for larger
algorithms
• Quad timer module can also be used for
simple digital-to-analog conversion
functionality
• Enhanced synchronous serial interface
with enhanced network and audio modes
• Time of Day for applications requiring
clock display
The 56853’s memory and peripheral set make it
ideal for a variety of applications, with a total of
four external timer outputs for the quad timer, an
additional SCI/UART, an 8-bit host interface and
6-channel direct memory access (DMA). Also, the
56853 offers an enhanced synchronous serial
interface (ESSI), with enhanced networking mode
and audio capabilities. The external memory
expansion is also increased for an additional 2 MB
of data addressing space. The 56853 also includes a
Time of Day module for applications, requiring clock
features. With the host interface and serial
peripherals, multiple 56853 devices can be designed
into a system to interface gluelessly with other
Motorola processors, such as the MPC8xx and
ColdFire processors, adding such DSP functionality
as voice processing to network applications.
The 56853 is available in a 128-pin LQFP package
and is an ideal stand-alone processor for client-side
telecom/datacom applications, requiring only a
few channels.
56853 16-BIT DIGITAL SIGNAL PROCESSORS
• 120 MIPS at 120MHz
• 24 KB Program SRAM
• 8 KB Data SRAM
• 2 KB Boot ROM
• Serial Peripheral Interface (SPI)
• 8-bit parallel Host Interface
• General purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation
(OnCETM) for unobtrusive, real-time
debugging
• Access up to 4 MB of program memory
or up to 16 MB of data memory
• Computer Operating Properly
(COP)/Watchdog Timer
• Chip Select Logic for glueless interface
to ROM and SRAM
• Time of Day (TOD)
• 128-pin LQFP package
• Up to 41 GPIO
• Six independent channels of DMA
• Enhanced Synchronous Serial Interfaces
(ESSI)
• Two Serial Communication Interfaces
(SCI)
ENERGY INFORMATION
• Fabricated in high-density CMOS with
3.3V, TTL-compatible digital inputs
• Wait and Stop modes available
Program Memory
COP/Watchdog
Ext Memory I/F
6-channel DMA
Prog Chip Selects
Up to 41 GPIO
24 KB SRAM
SPI
2 KB Boot ROM
(2) SCI
ESSI
56800E Core
16-Bit Quad Timer
Time of Day
120 MIPS
Data Memory
PLL
For More Information On This Product,
8 KB SRAM
Go to: www.freescale.com
8-Bit Host
JTAG/EOnCE