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DSP56854FG120 PDF预览

DSP56854FG120

更新时间: 2024-09-24 20:15:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
52页 584K
描述
Digital Signal Processor, 16-Bit Size, 16-Ext Bit, 240MHz, CMOS, PQFP128, LQFP-128

DSP56854FG120 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP, QFP128,.63X.87,20针数:128
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.28
Is Samacsys:N其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:21桶式移位器:YES
边界扫描:YES最大时钟频率:240 MHz
外部数据总线宽度:16格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:R-PQFP-G128
长度:20 mm低功率模式:YES
端子数量:128最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:1.98 V
最小供电电压:1.62 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

DSP56854FG120 数据手册

 浏览型号DSP56854FG120的Datasheet PDF文件第2页浏览型号DSP56854FG120的Datasheet PDF文件第3页浏览型号DSP56854FG120的Datasheet PDF文件第4页浏览型号DSP56854FG120的Datasheet PDF文件第5页浏览型号DSP56854FG120的Datasheet PDF文件第6页浏览型号DSP56854FG120的Datasheet PDF文件第7页 
DSP56854/D  
Rev. 2.0 3/2003  
DSP56854  
Preliminary Technical Data  
DSP56854 16-bit Digital Signal Processor  
• 120 MIPS at 120MHz  
• Serial Port Interface (SPI)  
• 16K x 16-bit Program SRAM  
• 16K x 16-bit Data SRAM  
• 1K x 16-bit Boot ROM  
• 8-bit Parallel Host Interface  
• General Purpose 16-bit Quad Timer  
• JTAG/Enhanced On-Chip Emulation (OnCE™) for  
unobtrusive, real-time debugging  
• Access up to 2M words of program or 8M data  
memory  
• Computer Operating Properly (COP)/Watchdog  
Timer  
• Chip Select Logic for glue-less interface to ROM  
and SRAM  
• Time-of-Day (TOD)  
• 128 LQFP package  
• Up to 41 GPIO  
• Six (6) independent channels of DMA  
• Enhanced Synchronous Serial Interfaces (ESSI)  
• Two (2) Serial Communication Interfaces (SCI)  
V
V
6
V
V
SSA  
V
V
SSIO  
SS  
DDA  
DDIO  
DD  
6
10  
11  
6
JTAG/  
Enhanced  
OnCE  
16-Bit  
DSP56800E Core  
Program Controller  
and  
Hardware Looping Unit  
Address  
Generation Unit  
Data ALU  
16 x 16 + 36 36-Bit MAC  
Three 16-bit Input Registers  
Four 36-bit Accumulators  
Bit  
Manipulation  
Unit  
PAB  
PDB  
CDBR  
CDBW  
Memory  
XDB2  
Program Memory  
XAB1  
16,384 x 16 SRAM  
XAB2  
System  
Bus  
Control  
DMA  
6 channel  
Boot ROM  
PAB  
1024 x 16 ROM  
PDB  
Data Memory  
16,384 x 16 SRAM  
CDBR  
CDBW  
IPBus Bridge (IPBB)  
Decoding  
Peripherals  
POR  
CLKO  
IPBus CLK  
3
MODEA-C or  
(GPIOH0-H2)  
System  
Integration  
Module  
COP/TOD CLK  
RSTO  
External Address  
Bus Switch  
A0-20 [20:0]  
RESET  
External Data  
Bus Switch  
External Bus  
Interface Unit  
D0-D15 [15:0]  
EXTAL  
XTAL  
Clock  
Generator  
ESSI0  
or  
GPIOC  
2 SCI  
or  
GPIOE  
Quad  
Timer  
or  
SPI  
or  
GPIOF  
Host  
Interrupt  
COP/  
Watch-  
dog  
Time  
of  
Day  
RD Enable  
WR Enable  
Interface Controller  
or  
GPIOB  
Bus Control  
OSC PLL  
GPIOG  
CS0-CS3[3:0] or  
GPIOA0-GPIOA3[3:0]  
6
4
4
4
16  
IRQA  
IRQB  
Figure 1. DSP56854 Block Diagram  
© Motorola, Inc., 2003. All rights reserved.  

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