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DS99R102VS/NOPB PDF预览

DS99R102VS/NOPB

更新时间: 2023-09-03 20:38:09
品牌 Logo 应用领域
德州仪器 - TI 接口集成电路
页数 文件大小 规格书
29页 615K
描述
3-40MHz 直流平衡 24 位 LVDS 解串器 | PFB | 48 | 0 to 70

DS99R102VS/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TFQFP, TQFP48,.35SQ
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.27差分输出:NO
接口集成电路类型:LINE RECEIVERJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
湿度敏感等级:3功能数量:1
端子数量:48最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP48,.35SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
接收器位数:1座面最大高度:1.2 mm
子类别:Line Driver or Receivers最大压摆率:85 mA
标称供电电压:3.3 V电源电压1-最大:3.6 V
电源电压1-分钟:3 V电源电压1-Nom:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

DS99R102VS/NOPB 数据手册

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DS99R101, DS99R102  
www.ti.com  
SNLS240D MARCH 2007REVISED APRIL 2013  
DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer  
Check for Samples: DS99R101, DS99R102  
1
FEATURES  
Receiver  
48-Pin TQFP Package  
2
3 MHz–40 MHz Clock Embedded and DC-  
Balancing 24:1 and 1:24 Data Transmissions  
Pure CMOS .35 μm Process  
Power Supply Range 3.3V ± 10%  
Temperature Range 0°C to +70°C  
8 kV HBM ESD Tolerance  
User Selectable Clock Edge for Parallel Data  
on Both Transmitter and Receiver  
Internal DC Balancing Encode/Decode –  
Supports AC-Coupling Interface with No  
External Coding Required  
DESCRIPTION  
Individual Power-Down Controls for Both  
Transmitter and Receiver  
The DS99R101/DS99R102 Chipset translates a 24-  
bit parallel bus into a fully transparent data/control  
LVDS serial stream with embedded clock information.  
This single serial stream simplifies transferring a 24-  
bit bus over PCB traces and cable by eliminating the  
skew problems between parallel data and clock  
paths. It saves system cost by narrowing data paths  
that in turn reduce PCB layers, cable width, and  
connector size and pins.  
Embedded Clock CDR (Clock and Data  
Recovery) on Receiver and No External Source  
of Reference Clock Needed  
All Codes RDL (Random Data Lock) to Support  
Live-Pluggable Applications  
LOCK Output Flag to Ensure Data Integrity at  
Receiver Side  
The DS99R101/DS99R102 incorporates LVDS  
signaling on the high-speed I/O. LVDS provides a low  
power and low noise environment for reliably  
transferring data over a serial transmission path. By  
optimizing the serializer output edge rate for the  
operating frequency range EMI is further reduced.  
Balanced TSETUP/THOLD Between RCLK and  
RDATA on Receiver Side  
PTO (Progressive Turn-On) LVCMOS Outputs  
to Reduce EMI and Minimize SSO Effects  
All LVCMOS Inputs and Control Pins Have  
Internal Pulldown  
Internal DC balanced encoding/decoding is used to  
support AC-Coupled interconnects.  
On-Chip Filters for PLLs on Transmitter and  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  

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