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DS99R103 PDF预览

DS99R103

更新时间： 2023-09-03 20:29:53
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
31页 730K
描述
适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVDS 串行器

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中文翻译

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DS99R103 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：7 X 7 MM, 1 MM HEIGHT, 0.50 MM PITCH, TQFP-48Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.43差分输出：YES
驱动器位数：1输入特性：DIFFERENTIAL
接口集成电路类型：LINE DRIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-PQFP-G48JESD-609代码：e0
长度：7 mm湿度敏感等级：1
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装等效代码：TQFP48,.35SQ封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：接收器位数：1
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：7 mm
Base Number Matches：1

DS99R103 数据手册

 浏览型号DS99R103的Datasheet PDF文件第2页浏览型号DS99R103的Datasheet PDF文件第3页浏览型号DS99R103的Datasheet PDF文件第4页浏览型号DS99R103的Datasheet PDF文件第5页浏览型号DS99R103的Datasheet PDF文件第6页浏览型号DS99R103的Datasheet PDF文件第7页 
DS99R103, DS99R104  
www.ti.com  
SNLS241D –MARCH 2007–REVISED APRIL 2013  
DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer  
Check for Samples: DS99R103, DS99R104  
1
FEATURES  
DESCRIPTION  
The DS99R103/DS99R104 Chipset translates a 24-  
bit parallel bus into a fully transparent data/control  
LVDS serial stream with embedded clock information.  
This single serial stream simplifies transferring a 24-  
bit bus over PCB traces and cable by eliminating the  
skew problems between parallel data and clock  
paths. It saves system cost by narrowing data paths  
that in turn reduce PCB layers, cable width, and  
connector size and pins.  
2
•
3 MHz–40 MHz Clock Embedded and DC-  
Balancing 24:1 and 1:24 Data Transmissions  
•
•
Capable to Drive Shielded Twisted-Pair Cable  
User Selectable Clock Edge for Parallel Data  
on both Transmitter and Receiver  
•
Internal DC Balancing Encode/Decode –  
Supports AC-Coupling Interface with no  
External Coding Required  
The DS99R103/DS99R104 incorporates LVDS  
signaling on the high-speed I/O. LVDS provides a low  
power and low noise environment for reliably  
transferring data over a serial transmission path. By  
optimizing the serializer output edge rate for the  
operating frequency range EMI is further reduced.  
•
•
Individual Power-Down Controls for both  
Transmitter and Receiver  
Embedded Clock CDR (Clock and Data  
Recovery) on Receiver and no External Source  
of Reference Clock Needed  
•
•
•
•
•
•
All Codes RDL (Random Data Lock) to Support  
Live-Pluggable Applications  
In addition the device features pre-emphasis to boost  
signals over longer distances using lossy cables.  
Internal DC balanced encoding/decoding is used to  
support AC-Coupled interconnects.  
LOCK Output Flag to Ensure Data Integrity at  
Receiver Side  
Balanced TSETUP/THOLD Between RCLK and  
RDATA on Receiver Side  
PTO (Progressive Turn-On) LVCMOS Outputs  
to Reduce EMI and Minimize SSO Effects  
All LVCMOS inputs and control pins have  
internal pulldown  
On-Chip Filters for PLLs on Transmitter and  
Receiver  
•
•
•
•
•
•
•
Integrated 100Ω Input Termination on Receiver  
4 mA Receiver Output Drive  
48-Pin TQFP and 48-Pin WQFN Packages  
Pure CMOS .35 μm Process  
Power Supply Range 3.3V ± 10%  
Temperature Range −40°C to +85°C  
8 kV HBM ESD Tolerance  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  
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