Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS99R106VS

DS99R106VS

更新时间： 2024-02-03 00:07:00

品牌	Logo	应用领域
美国国家半导体 - NSC		驱动器接口集成电路
页数	文件大小	规格书
24页	922K
描述
3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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中文翻译

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数据手册

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DS99R106VS 数据手册

October 2007

DS99R105/DS99R106

3-40MHz DC-Balanced 24-Bit LVDS Serializer and

Deserializer

General Description

The DS99R105/DS99R106 Chipset translates a 24-bit paral-

lel bus into a fully transparent data/control LVDS serial stream

with embedded clock information. This single serial stream

simplifies transferring a 24-bit bus over PCB traces and cable

by eliminating the skew problems between parallel data and

clock paths. It saves system cost by narrowing data paths that

in turn reduce PCB layers, cable width, and connector size

and pins.

Internal DC Balancing encode/decode – Supports AC-

coupling interface with no external coding required

Individual power-down controls for both Transmitter and

Receiver

Embedded clock CDR (clock and data recovery) on

Receiver and no external source of reference clock

needed

All codes RDL (random data lock) to support live-

pluggable applications

■

LOCK output flag to ensure data integrity at Receiver side

■

The DS99R105/DS99R106 incorporates LVDS signaling on

the high-speed I/O. LVDS provides a low power and low noise

environment for reliably transferring data over a serial trans-

mission path. By optimizing the serializer output edge rate for

the operating frequency range EMI is further reduced.

Balanced T_SETUP/T_HOLDbetween RCLK and RDATA on

Receiver side

PTO (progressive turn-on) LVCMOS outputs to reduce

EMI and minimize SSO effects

All LVCMOS inputs and control pins have internal

pulldown

On-chip filters for PLLs on Transmitter and Receiver

Integrated 100Ω input termination on Receiver

4 mA Receiver output drive

■

In addition the device features pre-emphasis to boost signals

over longer distances using lossy cables. Internal DC bal-

anced encoding/decoding is used to support AC-Coupled

interconnects.

■

Features

48-pin TQFP and 48-pin LLP packages

Pure CMOS .35 μm process

Power supply range 3.3V ± 10%

Temperature range 0°C to +70°C

8 kV HBM ESD tolerance

3 MHz–40 MHz clock embedded and DC-Balancing 24:1

and 1:24 data transmissions

■

Capable to drive shielded twisted-pair cable

■

User selectable clock edge for parallel data on both

Transmitter and Receiver

Block Diagram

20208101

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

202081

www.national.com

12 3 4 5 6 7...24

中文翻译

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与DS99R106VS相关器件

型号	品牌	获取价格	描述	数据表
DS99R106VS/NOPB	NSC	获取价格	IC LINE TRANSCEIVER, PQFP48, 7 X 7 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, TQFP-48, Line Dr
DS99R106VS/NOPB	TI	获取价格	3MHz 至 40MHz 直流平衡 24 位 LVDS 解串器 \| PFB \| 48 \|
DS99R106VSX	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R106VSX/NOPB	NSC	获取价格	IC LINE TRANSCEIVER, PQFP48, 7 X 7 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, TQFP-48, Line Dr
DS99R124AQ	TI	获取价格	DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
DS99R124AQ-Q1	TI	获取价格	5MHz 至 43MHz 18 位彩色 FPD-Link II 至 FPD-Link 转换
DS99R124AQSQ	TI	获取价格	DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
DS99R124AQSQ/NOPB	TI	获取价格	5MHz 至 43MHz 18 位彩色 FPD-Link II 至 FPD-Link 转换
DS99R124AQSQE	TI	获取价格	DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
DS99R124AQSQE/NOPB	TI	获取价格	5MHz 至 43MHz 18 位彩色 FPD-Link II 至 FPD-Link 转换

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