Datasheet > DS99R103_0710

DS99R103_0710

更新时间： 2024-01-25 10:56:24

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
24页	924K
描述
3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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中文翻译

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DS99R103_0710 数据手册

October 2007

DS99R103/DS99R104

3-40MHz DC-Balanced 24-Bit LVDS Serializer and

Deserializer

General Description

The DS99R103/DS99R104 Chipset translates a 24-bit paral-

lel bus into a fully transparent data/control LVDS serial stream

with embedded clock information. This single serial stream

simplifies transferring a 24-bit bus over PCB traces and cable

by eliminating the skew problems between parallel data and

clock paths. It saves system cost by narrowing data paths that

in turn reduce PCB layers, cable width, and connector size

and pins.

Internal DC Balancing encode/decode – Supports AC-

coupling interface with no external coding required

Individual power-down controls for both Transmitter and

Receiver

Embedded clock CDR (clock and data recovery) on

Receiver and no external source of reference clock

needed

All codes RDL (random data lock) to support live-

pluggable applications

■

LOCK output flag to ensure data integrity at Receiver side

■

The DS99R103/DS99R104 incorporates LVDS signaling on

the high-speed I/O. LVDS provides a low power and low noise

environment for reliably transferring data over a serial trans-

mission path. By optimizing the serializer output edge rate for

the operating frequency range EMI is further reduced.

Balanced T_SETUP/T_HOLDbetween RCLK and RDATA on

Receiver side

PTO (progressive turn-on) LVCMOS outputs to reduce

EMI and minimize SSO effects

All LVCMOS inputs and control pins have internal

pulldown

On-chip filters for PLLs on Transmitter and Receiver

Integrated 100Ω input termination on Receiver

4 mA Receiver output drive

■

In addition the device features pre-emphasis to boost signals

over longer distances using lossy cables. Internal DC bal-

anced encoding/decoding is used to support AC-Coupled

interconnects.

■

Features

48-pin TQFP and 48-pin LLP packages

Pure CMOS .35 μm process

Power supply range 3.3V ± 10%

3 MHz–40 MHz clock embedded and DC-Balancing 24:1

and 1:24 data transmissions

■

Capable to drive shielded twisted-pair cable

■

Temperature range −40°C to +85°C

8 kV HBM ESD tolerance

User selectable clock edge for parallel data on both

Transmitter and Receiver

Block Diagram

20208001

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

202080

www.national.com

12 3 4 5 6 7...24

中文翻译

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与DS99R103_0710相关器件

型号	品牌	获取价格	描述	数据表
DS99R103TSQ	ROCHESTER	获取价格	LINE DRIVER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48
DS99R103TSQ/NOPB	TI	获取价格	适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD
DS99R103TSQX	NSC	获取价格	暂无描述
DS99R103TSQX/NOPB	TI	获取价格	适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD
DS99R103TVS	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R103TVS/NOPB	TI	获取价格	适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD
DS99R103TVSX	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R104	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R104	TI	获取价格	适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD
DS99R104TSQ/NOPB	TI	获取价格	适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD

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