Datasheet > DS99R101VS/NOPB

DS99R101VS/NOPB

更新时间： 2023-09-03 20:27:10

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
29页	615K
描述
3-40MHz 直流平衡 24 位 LVDS 串行器 \| PFB \| 48 \| 0 to 70

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DS99R101VS/NOPB 数据手册

DS99R101, DS99R102

www.ti.com

SNLS240D –MARCH 2007–REVISED APRIL 2013

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Check for Samples: DS99R101, DS99R102

FEATURES

Receiver

•

48-Pin TQFP Package

•

3 MHz–40 MHz Clock Embedded and DC-

Balancing 24:1 and 1:24 Data Transmissions

Pure CMOS .35 μm Process

Power Supply Range 3.3V ± 10%

Temperature Range 0°C to +70°C

8 kV HBM ESD Tolerance

•

User Selectable Clock Edge for Parallel Data

on Both Transmitter and Receiver

Internal DC Balancing Encode/Decode –

Supports AC-Coupling Interface with No

External Coding Required

DESCRIPTION

•

Individual Power-Down Controls for Both

Transmitter and Receiver

The DS99R101/DS99R102 Chipset translates a 24-

bit parallel bus into a fully transparent data/control

LVDS serial stream with embedded clock information.

This single serial stream simplifies transferring a 24-

bit bus over PCB traces and cable by eliminating the

skew problems between parallel data and clock

paths. It saves system cost by narrowing data paths

that in turn reduce PCB layers, cable width, and

connector size and pins.

Embedded Clock CDR (Clock and Data

Recovery) on Receiver and No External Source

of Reference Clock Needed

•

All Codes RDL (Random Data Lock) to Support

Live-Pluggable Applications

LOCK Output Flag to Ensure Data Integrity at

Receiver Side

The DS99R101/DS99R102 incorporates LVDS

signaling on the high-speed I/O. LVDS provides a low

power and low noise environment for reliably

transferring data over a serial transmission path. By

optimizing the serializer output edge rate for the

operating frequency range EMI is further reduced.

Balanced T_SETUP/T_HOLDBetween RCLK and

RDATA on Receiver Side

PTO (Progressive Turn-On) LVCMOS Outputs

to Reduce EMI and Minimize SSO Effects

All LVCMOS Inputs and Control Pins Have

Internal Pulldown

Internal DC balanced encoding/decoding is used to

support AC-Coupled interconnects.

On-Chip Filters for PLLs on Transmitter and

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...29

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与DS99R101VS/NOPB相关器件

型号	品牌	获取价格	描述	数据表
DS99R101VSX	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R102	TI	获取价格	3-40MHz 直流平衡 24 位 LVDS 解串器
DS99R102VS	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R102VS/NOPB	TI	获取价格	3-40MHz 直流平衡 24 位 LVDS 解串器 \| PFB \| 48 \| 0 to
DS99R102VSX	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R103	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R103	TI	获取价格	适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD
DS99R103_0710	NSC	获取价格	3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R103TSQ	ROCHESTER	获取价格	LINE DRIVER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48
DS99R103TSQ/NOPB	TI	获取价格	适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD

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