5秒后页面跳转
捷配首页

Datasheet > DS99R101
DS99R101 PDF预览

DS99R101

更新时间： 2023-09-03 20:27:10
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
29页 615K
描述
3-40MHz 直流平衡 24 位 LVDS 串行器

阅读下载

中文翻译

获取价格

DS99R101 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：7 X 7 MM, 1 MM HEIGHT, 0.50 MM PITCH, TQFP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.43
Is Samacsys：N差分输出：YES
驱动器位数：1输入特性：DIFFERENTIAL
接口集成电路类型：LINE DRIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-PQFP-G48JESD-609代码：e0
长度：7 mm湿度敏感等级：3
功能数量：1端子数量：48
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
接收器位数：1座面最大高度：1.2 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：7 mm
Base Number Matches：1

DS99R101 数据手册

 浏览型号DS99R101的Datasheet PDF文件第2页浏览型号DS99R101的Datasheet PDF文件第3页浏览型号DS99R101的Datasheet PDF文件第4页浏览型号DS99R101的Datasheet PDF文件第5页浏览型号DS99R101的Datasheet PDF文件第6页浏览型号DS99R101的Datasheet PDF文件第7页 
DS99R101, DS99R102  
www.ti.com  
SNLS240D –MARCH 2007–REVISED APRIL 2013  
DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer  
Check for Samples: DS99R101, DS99R102  
1
FEATURES  
Receiver  
•
•
•
•
•
48-Pin TQFP Package  
2
•
3 MHz–40 MHz Clock Embedded and DC-  
Balancing 24:1 and 1:24 Data Transmissions  
Pure CMOS .35 μm Process  
Power Supply Range 3.3V ± 10%  
Temperature Range 0°C to +70°C  
8 kV HBM ESD Tolerance  
•
•
User Selectable Clock Edge for Parallel Data  
on Both Transmitter and Receiver  
Internal DC Balancing Encode/Decode –  
Supports AC-Coupling Interface with No  
External Coding Required  
DESCRIPTION  
•
•
Individual Power-Down Controls for Both  
Transmitter and Receiver  
The DS99R101/DS99R102 Chipset translates a 24-  
bit parallel bus into a fully transparent data/control  
LVDS serial stream with embedded clock information.  
This single serial stream simplifies transferring a 24-  
bit bus over PCB traces and cable by eliminating the  
skew problems between parallel data and clock  
paths. It saves system cost by narrowing data paths  
that in turn reduce PCB layers, cable width, and  
connector size and pins.  
Embedded Clock CDR (Clock and Data  
Recovery) on Receiver and No External Source  
of Reference Clock Needed  
•
•
•
•
•
•
All Codes RDL (Random Data Lock) to Support  
Live-Pluggable Applications  
LOCK Output Flag to Ensure Data Integrity at  
Receiver Side  
The DS99R101/DS99R102 incorporates LVDS  
signaling on the high-speed I/O. LVDS provides a low  
power and low noise environment for reliably  
transferring data over a serial transmission path. By  
optimizing the serializer output edge rate for the  
operating frequency range EMI is further reduced.  
Balanced TSETUP/THOLD Between RCLK and  
RDATA on Receiver Side  
PTO (Progressive Turn-On) LVCMOS Outputs  
to Reduce EMI and Minimize SSO Effects  
All LVCMOS Inputs and Control Pins Have  
Internal Pulldown  
Internal DC balanced encoding/decoding is used to  
support AC-Coupled interconnects.  
On-Chip Filters for PLLs on Transmitter and  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  
1234567...29

中文翻译

下载PDF

与DS99R101相关器件

型号 品牌 获取价格 描述 数据表
DS99R101VS NSC

获取价格

 		3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R101VS/NOPB TI

获取价格

 		3-40MHz 直流平衡 24 位 LVDS 串行器 | PFB | 48 | 0 to
DS99R101VSX NSC

获取价格

 		3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R102 TI

获取价格

 		3-40MHz 直流平衡 24 位 LVDS 解串器
DS99R102VS NSC

获取价格

 		3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R102VS/NOPB TI

获取价格

 		3-40MHz 直流平衡 24 位 LVDS 解串器 | PFB | 48 | 0 to
DS99R102VSX NSC

获取价格

 		3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R103 NSC

获取价格

 		3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R103 TI

获取价格

 		适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVD
DS99R103_0710 NSC

获取价格

 		3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

与DS99R101相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证