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DS92LV040ATLQAX PDF预览

DS92LV040ATLQAX

更新时间: 2024-01-27 20:31:20
品牌 Logo 应用领域
美国国家半导体 - NSC 总线收发器
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12页 219K
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DS92LV040ATLQAX 数据手册

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August 2002  
DS92LV040A  
4 Channel Bus LVDS Transceiver  
General Description  
Features  
n Bus LVDS Signaling  
The DS92LV040A is one in a series of Bus LVDS transceiv-  
ers designed specifically for high speed, low power back-  
plane or cable interfaces. The device operates from a single  
3.3V power supply and includes four differential line drivers  
and four receivers. To minimize bus loading, the driver out-  
puts and receiver inputs are internally connected. The device  
also features a flow through pin out which allows easy PCB  
routing for short stubs between its pins and the connector.  
n Propagation delay: Driver 2.3ns max, Receiver 3.2ns  
max  
n Low power CMOS design  
n 100% Transition time 1ns driver typical, 1.3ns receiver  
typical  
n High Signaling Rate Capability (above 155 Mbps)  
n 0.1V to 2.3V Common Mode Range for VID = 200mV  
n 70 mV Receiver Sensitivity  
n Supports open and terminated failsafe on port pins  
n 3.3V operation  
n Glitch free power up/down (Driver & Receiver disabled)  
n Light Bus Loading (5 pF typical) per Bus LVDS load  
n Designed for Double Termination Applications  
n Balanced Output Impedance  
The driver translates 3V LVTTL levels (single-ended) to dif-  
ferential Bus LVDS (BLVDS) output levels. This allows for  
high speed operation while consuming minimal power and  
reducing EMI. In addition, the differential signaling provides  
common mode noise rejection greater than 1V.  
The receiver threshold is less than +0/−70 mV. The receiver  
translates the differential Bus LVDS to standard (LVTTL/  
LVCMOS) levels. (See Applications Information Section for  
more details.)  
n Product offered in 44 pin LLP (Leadless Leadframe  
Package) package  
n High impedance Bus pins on power off (VCC = 0V)  
Simplified Functional Diagram  
10133601  
© 2002 National Semiconductor Corporation  
DS101336  
www.national.com  

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