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DS90UB902Q-Q1 PDF预览

DS90UB902Q-Q1

更新时间: 2024-11-17 11:07:51
品牌 Logo 应用领域
德州仪器 - TI 光电二极管
页数 文件大小 规格书
45页 1109K
描述
具有双向控制通道的 10 - 43MHz 14 位色彩 FPD-Link III 解串器

DS90UB902Q-Q1 数据手册

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April 25, 2012  
DS90UB901Q/DS90UB902Q  
10 - 43MHz 14 Bit Color FPD-Link III Serializer and  
Deserializer with Bidirectional Control Channel  
Single differential pair interconnect  
Bidirectional control interface channel with I2C support  
General Description  
The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link  
III interface with a high-speed forward channel and a bidirec-  
tional control channel for data transmission over a single  
differential pair. The Serializer/Deserializer pair is targeted for  
direct connections between automotive camera systems and  
Host Controller/Electronic Control Unit (ECU). The primary  
transport sends 16 bits of image data over a single high-speed  
serial stream together with a low latency bidirectional control  
channel transport that supports I2C. Included with the 16-bit  
payload is a selectable data integrity option for CRC (Cyclic  
Redundancy Check) to monitor transmission link errors. Us-  
ing TI’s embedded clock technology allows transparent full-  
duplex communication over a single differential pair, carrying  
asymmetrical bidirectional control information without the de-  
pendency of video blanking intervals. This single serial  
stream simplifies transferring a wide data bus over PCB  
traces and cable by eliminating the skew problems between  
parallel data and clock paths. This significantly saves system  
cost by narrowing data paths that in turn reduce PCB layers,  
cable width, and connector size and pins.  
Embedded clock with DC Balanced coding to support AC-  
coupled interconnects  
Capable to drive up to 10 meters shielded twisted-pair  
I2C compatible serial interface  
Single hardware device addressing pin  
16–bit data payload with CRC (Cyclic Redundancy Check)  
for checking data integrity  
Up to 6 Programmable GPIO's  
LOCK output reporting pin and AT-SPEED BIST diagnosis  
feature to validate link integrity  
Integrated termination resistors  
1.8V- or 3.3V-compatible parallel bus interface  
Single power supply at 1.8V  
ISO 10605 ESD and IEC 61000-4-2 ESD compliant  
Automotive grade product: AEC-Q100 Grade 2 qualified  
Temperature range −40°C to +105°C  
No reference clock required on Deserializer  
Programmable Receive Equalization  
EMI/EMC Mitigation  
In addition, the Deserializer inputs provide equalization con-  
trol to compensate for loss from the media over longer dis-  
tances. Internal DC balanced encoding/decoding is used to  
support AC-Coupled interconnects.  
DES Programmable Spread Spectrum (SSCG)  
outputs  
A Serializer standby function provides a low power-savings  
mode with a remote wake up capability for signaling of a re-  
mote device.  
DES Receiver staggered outputs  
Applications  
The Serializer is offered in a 32-pin LLP (5mm x 5mm) pack-  
age, and Deserializer is offered in a 40-pin LLP (6mm x 6mm)  
package.  
Automotive Vision Systems  
Rear View, Side View Camera  
Lane Departure Warning  
Features  
Parking Assistance  
10 MHz to 43 MHz input PCLK support  
Blind Spot View  
160 Mbps to 688 Mbps data throughput  
Typical Application Diagram  
30113527  
FIGURE 1. Typical Application Circuit  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2012 Texas Instruments Incorporated  
301135 SNLS322D  
www.ti.com  

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具有双向控制通道的 10 - 43MHz 14 位色彩 FPD-Link III 解串器