April 25, 2012
DS90UB903Q/DS90UB904Q
10 - 43MHz 18 Bit Color FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Single differential pair interconnect
Bidirectional control interface channel with I2C support
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General Description
The DS90UB903Q/DS90UB904Q chipset offers a FPD-Link
III interface with a high-speed forward channel and a bidirec-
tional control channel for data transmission over a single
differential pair. The DS90UB903Q/904Q incorporates differ-
ential signaling on both the high-speed forward channel and
bidirectional control channel data paths. The Serializer/ De-
serializer pair is targeted for direct connections between
graphics host controller and displays modules. This chipset is
ideally suited for driving video data to displays requiring 18-
bit color depth (RGB666 + HS, VS, and DE) along with
bidirectional control channel bus. The primary transport con-
verts 21 bit data over a single high-speed serial stream, along
with a separate low latency bidirectional control channel
transport that accepts control information from an I2C port.
Using TI’s embedded clock technology allows transparent
full-duplex communication over a single differential pair, car-
rying asymmetrical bidirectional control channel information
in both directions. This single serial stream simplifies trans-
ferring a wide data bus over PCB traces and cable by elimi-
nating the skew problems between parallel data and clock
paths. This significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width, and con-
nector size and pins.
Embedded clock with DC Balanced coding to support AC-
coupled interconnects
Capable to drive up to 10 meters shielded twisted-pair
I2C compatible serial interface
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Single hardware device addressing pin
Up to 4 General Purpose Input (GPI)/ Output (GPO)
LOCK output reporting pin and AT-SPEED BIST diagnosis
feature to validate link integrity
Integrated termination resistors
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1.8V- or 3.3V-compatible parallel bus interface
Single power supply at 1.8V
ISO 10605 ESD and IEC 61000-4-2 ESD compliant
Automotive grade product: AEC-Q100 Grade 2 qualified
Temperature range −40°C to +105°C
No reference clock required on Deserializer
Programmable Receive Equalization
EMI/EMC Mitigation
DES Programmable Spread Spectrum (SSCG)
outputs
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DES Receiver staggered outputs
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In addition, the Deserializer inputs provide equalization con-
trol to compensate for loss from the media over longer dis-
tances. Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects.
Applications
Automotive Display Systems
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The Serializer is offered in a 40-pin lead in LLP and Deseri-
alizer is offered in a 48-pin LLP packages.
Central Information Displays
Navigation Displays
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Rear Seat Entertainment
Touch Screen Displays
Features
10 MHz to 43 MHz input PCLK support
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210 Mbps to 903 Mbps data throughput
Typical Application Diagram
30125427
FIGURE 1. Typical Application Circuit
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© 2012 Texas Instruments Incorporated
301254 SNLS332D
www.ti.com