Datasheet > DS90C365A_05

DS90C365A_05

更新时间： 2024-09-30 04:39:11

品牌	Logo	应用领域
美国国家半导体 - NSC		显示器
页数	文件大小	规格书
12页	621K
描述
+3.3V programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

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DS90C365A_05 数据手册

PRELIMINARY

October 2005

DS90C365A

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel

Display Link-87.5 MHz

General Description

Features

n Pin-to-pin compatible to DS90C363, DS90C363A and

DS90C365 .

The DS90C365A is a pin to pin compatible replacement for

DS90C363, DS90C363A and DS90C365. The DS90C365A

has additional features and improvements making it an ideal

replacement for DS90C363, DS90C363A and DS90C365.

family of LVDS Transmitters.

n No special start-up sequence required between

clock/data and /PD pins. Input signals (clock and data)

can be applied either before or after the device is

powered.

The DS90C365A transmitter converts 21 bits of LVCMOS/

LVTTL data into four LVDS (Low Voltage Differential Signal-

ing) data streams. A phase-locked transmit clock is transmit-

ted in parallel with the data streams over the fourth LVDS

link. Every cycle of the transmit clock 21 bits RGB of input

data are sampled and transmitted. At a transmit clock fre-

quency of 87.5 MHz, 21 bits of RGB data and 3 bits of LCD

timing and control data (FPLINE, FPFRAME, DRDY) are

transmitted at a rate of 612.5 Mbps per LVDS data channel.

Using a 87.5 MHz clock, the data throughput is 229.687

Mbytes/sec. This transmitter can be programmed for Rising

edge strobe or Falling edge strobe through a dedicated pin.

A Rising edge or Falling edge strobe transmitter will interop-

erate with a Falling edge strobe FPDLink Receiver without

any translation logic.

n Support Spread Spectrum Clocking up to 100kHz

frequency modulation & deviations of 2.5% center

spread or -5% down spread.

n “Input Clock Detection” feature will pull all LVDS pairs to

logic low when input clock is missing and when /PD pin

is logic high.

n 18 to 87.5 MHz shift clock support

n Tx power consumption 146 mW (typ) 87.5 MHz

Grayscale

n Tx Power-down mode 37 uW (typ)

n Supports VGA, SVGA, XGA, SXGA(dual pixel),

SXGA+(dual pixel), UXGA(dual pixel).

n Narrow bus reduces cable size and cost

n Up to 1.785 Gbps throughput

n Up to 223.125 Megabytes/sec bandwidth

n 345 mV (typ) swing LVDS devices for low EMI

n PLL requires no external components

n Compliant to TIA/EIA-644 LVDS standard

n Low profile 48-lead TSSOP package

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high-speed TTL interfaces

with added Spead Spectrum Clocking support..

Block Diagram

DS90C365A

20100539

Order Number DS90C365AMT

See NS Package Number MTD48

DS201005

www.national.com

12 3 4 5 6 7...12

中文翻译

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与DS90C365A_05相关器件

型号	品牌	获取价格	描述	数据表
DS90C365AMT	NSC	获取价格	+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-85 MHz
DS90C365AMT/NOPB	TI	获取价格	+3.3V 可编程 LVDS 发送器 18 位平板显示器链路 - 87.5MHz \| DG
DS90C365AMT/NOPB	NSC	获取价格	IC QUAD LINE DRIVER, PDSO48, TSSOP-48, Line Driver or Receiver
DS90C365AMTX	TI	获取价格	3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz
DS90C365AMTX/NOPB	TI	获取价格	+3.3V 可编程 LVDS 发送器 18 位平板显示器链路 - 87.5MHz \| DG
DS90C365MTD	NSC	获取价格	+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V Pro
DS90C365MTD	TI	获取价格	QUAD LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90C365MTDX	ROCHESTER	获取价格	QUAD LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90C365MTDX	TI	获取价格	QUAD LINE DRIVER, PDSO48, PLASTIC, TSSOP-48
DS90C383	NSC	获取价格	+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVD

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