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DS90C365AMT/NOPB PDF预览

DS90C365AMT/NOPB

更新时间: 2024-02-28 06:16:00
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
14页 251K
描述
IC QUAD LINE DRIVER, PDSO48, TSSOP-48, Line Driver or Receiver

DS90C365AMT/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TSSOP, TSSOP48,.3,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.1差分输出:YES
驱动器位数:4输入特性:STANDARD
接口集成电路类型:LINE DRIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:12.5 mm湿度敏感等级:2
功能数量:4端子数量:48
最高工作温度:70 °C最低工作温度:-10 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
最大接收延迟:座面最大高度:1.1 mm
子类别:Line Driver or Receivers最大压摆率:60 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:6.1 mm
Base Number Matches:1

DS90C365AMT/NOPB 数据手册

 浏览型号DS90C365AMT/NOPB的Datasheet PDF文件第2页浏览型号DS90C365AMT/NOPB的Datasheet PDF文件第3页浏览型号DS90C365AMT/NOPB的Datasheet PDF文件第4页浏览型号DS90C365AMT/NOPB的Datasheet PDF文件第5页浏览型号DS90C365AMT/NOPB的Datasheet PDF文件第6页浏览型号DS90C365AMT/NOPB的Datasheet PDF文件第7页 
August 6, 2008  
DS90C365A  
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel  
Display Link-87.5 MHz  
General Description  
Features  
The DS90C365A is a pin to pin compatible replacement for  
DS90C363, DS90C363A and DS90C365. The DS90C365A  
has additional features and improvements making it an ideal  
replacement for DS90C363, DS90C363A and DS90C365.  
family of LVDS Transmitters.  
Pin-to-pin compatible to DS90C363, DS90C363A and  
DS90C365 .  
No special start-up sequence required between clock/data  
and /PD pins. Input signals (clock and data) can be applied  
either before or after the device is powered.  
The DS90C365A transmitter converts 21 bits of LVCMOS/  
LVTTL data into four LVDS (Low Voltage Differential Signal-  
ing) data streams. A phase-locked transmit clock is transmit-  
ted in parallel with the data streams over the fourth LVDS link.  
Every cycle of the transmit clock 21 bits RGB of input data are  
sampled and transmitted. At a transmit clock frequency of  
87.5 MHz, 21 bits of RGB data and 3 bits of LCD timing and  
control data (FPLINE, FPFRAME, DRDY) are transmitted at  
a rate of 612.5 Mbps per LVDS data channel. Using a 87.5  
MHz clock, the data throughput is 229.687 Mbytes/sec. This  
transmitter can be programmed for Rising edge strobe or  
Falling edge strobe through a dedicated pin. A Rising edge or  
Falling edge strobe transmitter will interoperate with a Falling  
edge strobe FPDLink Receiver without any translation logic.  
Support Spread Spectrum Clocking up to 100kHz  
frequency modulation & deviations of ±2.5% center  
spread or -5% down spread.  
Input Clock Detection” feature will pull all LVDS pairs to  
logic low when input clock is missing and when /PD pin is  
logic high.  
18 to 87.5 MHz shift clock support  
Tx power consumption < 146 mW (typ) @ 87.5 MHz  
Grayscale  
Tx Power-down mode < 37 uW (typ)  
Supports VGA, SVGA, XGA, SXGA(dual pixel), SXGA+  
(dual pixel), UXGA(dual pixel).  
Narrow bus reduces cable size and cost  
Up to 1.785 Gbps throughput  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high-speed TTL interfaces  
with added Spead Spectrum Clocking support..  
Up to 223.125 Megabytes/sec bandwidth  
345 mV (typ) swing LVDS devices for low EMI  
PLL requires no external components  
Compliant to TIA/EIA-644 LVDS standard  
Low profile 48-lead TSSOP package  
Block Diagram  
DS90C365A  
20100539  
Order Number DS90C365AMT  
See NS Package Number MTD48  
© 2008 National Semiconductor Corporation  
201005  
www.national.com  

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