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DS90C383B PDF预览

DS90C383B

更新时间: 2024-02-16 03:51:53
品牌 Logo 应用领域
美国国家半导体 - NSC 显示器光电二极管
页数 文件大小 规格书
11页 639K
描述
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

DS90C383B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:LFBGA, BGA64,8X8,32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.54差分输出:YES
驱动器位数:4输入特性:STANDARD
接口集成电路类型:LINE DRIVER接口标准:EIA-644; TIA-644
JESD-30 代码:S-PBGA-B64JESD-609代码:e0
长度:8 mm功能数量:4
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA64,8X8,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:1.5 mm子类别:Line Driver or Receivers
最大压摆率:55 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

DS90C383B 数据手册

 浏览型号DS90C383B的Datasheet PDF文件第2页浏览型号DS90C383B的Datasheet PDF文件第3页浏览型号DS90C383B的Datasheet PDF文件第4页浏览型号DS90C383B的Datasheet PDF文件第5页浏览型号DS90C383B的Datasheet PDF文件第6页浏览型号DS90C383B的Datasheet PDF文件第7页 
October 2006  
DS90C383B  
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel  
Display (FPD) Link-65 MHz  
General Description  
Features  
n No special start-up sequence required between  
clock/data and /PD pins. Input signal (clock and data)  
can be applied either before or after the device is  
powered.  
The DS90C383B transmitter converts 28 bits of CMOS/TTL  
data into four LVDS (Low Voltage Differential Signaling) data  
streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fifth LVDS link. Every  
cycle of the transmit clock 28 bits of input data are sampled  
and transmitted. At a transmit clock frequency of 65 MHz, 24  
bits of RGB data and 3 bits of LCD timing and control data  
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455  
Mbps per LVDS data channel. Using a 65 MHz clock, the  
data throughput is 227 Mbytes/sec. The DS90C383B trans-  
mitter can be programmed for Rising edge strobe or Falling  
edge strobe through a dedicated pin. A Rising edge or  
Falling edge strobe transmitter will interoperate with a Falling  
edge strobe Receiver (DS90CF386) without any translation  
logic.  
n Support Spread Spectrum Clocking up to 100kHz  
frequency modulation & deviations of 2.5% center  
spread or −5% down spread.  
n "Input Clock Detection" feature will pull all LVDS pairs to  
logic low when input clock is missing and when /PD pin  
is logic high.  
n 18 to 68 MHz shift clock support  
n Best–in–Class Set & Hold Times on TxINPUTs  
n Tx power consumption 130 mW (typ) 65MHz  
Grayscale  
n 40% Less Power Dissipation than BiCMOS Alternatives  
<
@
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
<
n Tx Power-down mode 60µW (typ)  
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.  
n Narrow bus reduces cable size and cost  
n Up to 1.8 Gbps throughput  
n Up to 227 Megabytes/sec bandwidth  
n 345 mV (typ) swing LVDS devices for low EMI  
n PLL requires no external components  
n Compatible with TIA/EIA-644 LVDS standard  
n Low profile 56-lead TSSOP package  
n Improved replacement for:  
SN75LVDS83, DS90C383A  
Block Diagram  
DS90C383B  
20098401  
Order Number DS90C383BMT  
See NS Package Number MTD56  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2006 National Semiconductor Corporation  
DS200984  
www.national.com  

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IC QUAD LINE DRIVER, PDSO56, PLASTIC, TSSOP-56, Line Driver or Receiver