Datasheet > DS8906N

DS8906N

更新时间： 2024-11-28 22:22:31

品牌	Logo	应用领域
美国国家半导体 - NSC		光电二极管
页数	文件大小	规格书
8页	163K
描述
AM/FM Digital Phase-Locked Loop Synthesizer

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DS8906N 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.86
其他特性：	ALSO REQUIRES 4.5V TO 6V SUPPLY	模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e0
长度：	26.0731 mm	功能数量：	1
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电流 (Isup)：	160 mA	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

DS8906N 数据手册

July 1986

DS8906 AM/FM Digital Phase-Locked Loop Synthesizer

General Description

The DS8906 is a PLL synthesizer designed specifically for

use in AM/FM radios. It contains the reference oscillator, a

The high speed charge pump consists of a switchable con-

stant current source ( 0.3 mA) and a switchable constant

current sink ( 0.3 mA). If the VCO frequency is low, the

phase comparator, a charge pump, a 120 MHz ECL/I L

dual modulus programmable divider, and a 20-bit shift regis-

ter/latch for serial data entry. The device is designed to

operate with a serial data controller generating the neces-

sary division codes for each frequency, and logic state infor-

mation for radio function inputs/outputs.

charge pump will source current, and sink current if the VCO

frequency is high.

A separate V

pin (typically drawing 1.5 mA) powers the

CCM

oscillator and reference chain to provide controller clocking

frequencies when the balance of the PLL is powered down.

The Colpitts reference oscillator for the PLL operates at 4

MHz. A chain of dividers is used to generate a 500 kHz

clock signal for the external controller. Additional dividers

generate a 12.5 kHz reference signal for FM and a 500 Hz

reference signal for AM/SW. One of these reference signals

is selected by the data from the controller for use by the

phase comparator. Additional dividers are used to generate

a 50 Hz timing signal used by the controller for ‘‘time-of-

day’’.

Features

Uses inexpensive 4 MHz reference crystal

capability greater than 120 MHz allows direct syn-

thesis at FM frequencies

FM resolution of 12.5 kHz allows usage of 10.7 MHz

ceramic filter distribution

Serial data entry for simplified control

50 Hz output for ‘‘time-of-day’’ reference with separate

Data is transferred between the frequency synthesizer and

the controller via a 3 wire bus system. This consists of a

data input line, an enable line and a clock line. When the

enable line is low, data can be shifted from the controller

into the frequency synthesizer. When the enable line is tran-

sitioned from low to high, data entry is disabled and data

present in the shift register is latched.

low power supply (V

)

CCM

6-open collector buffered outputs for band switching

and other radio functions

Separate AM and FM inputs. AM input has 15 mV (typi-

cal) hysteresis

Connection Diagram

From the controller 22-bit data stream, the first 2 bits ad-

dress the device permitting other devices to share the same

bus. Of the remaining 20-bit data word, the next 14-bits are

used for the PLL divide code. The remaining 6 bits are con-

nected via latches to output pins. These 6 bits can be used

to drive radio functions such as gain, mute, FM, AM, LW and

SW only. These outputs are open collector. Bit 18 is used

internally to select the AM or FM local oscillator input and to

select between the 500 Hz and 12.5 kHz reference. A high

level at bit 18 indicates FM and a low level indicates AM.

Dual-In-Line Package

The PLL consists of a 14-bit programmable I L divider, an

ECL phase comparator, an ECL dual modulus (p/p

prescaler, and a high speed charge pump. The programma-

ble divider divides by (N 1), N being the number loaded

into the shift register (bits 1–14 after address). It is clocked

7/8 prescaler, or through a

by the AM input via an ECL

63/64 prescaler from the FM input. The AM input will work

at frequencies up to 8 MHz, while the FM input works up to

120 MHz. The AM band is tuned with a frequency resolution

of 500 Hz and the FM band is tuned with a resolution of 12.5

kHz. The buffered AM and FM inputs are self-biased and

can be driven directly by the VCO thru a capacitor. The ECL

phase comparator produces very accurate resolution of the

phase difference between the input signal and the reference

oscillator.

TL/F/5775–1

Top View

Order Number DS8906N

See NS Package Number N20A

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation

TL/F/5775

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7 8

中文翻译

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与DS8906N相关器件

型号	品牌	获取价格	描述	数据表
DS8906N/A+	ETC	获取价格	AM/FM Receiver Circuit
DS8906N/B+	ETC	获取价格	AM/FM Receiver Circuit
DS8907	NSC	获取价格	Phase-Locked Loop Frequency Synthesizer
DS8907J	NSC	获取价格	IC,RADIO RECEIVER CKT,AM/FM,BIPOLAR,DIP,20PIN,CERAMIC
DS8907J/A+	ETC	获取价格	AM/FM Receiver Circuit
DS8907N	NSC	获取价格	Phase-Locked Loop Frequency Synthesizer
DS8907N/A+	ETC	获取价格	AM/FM Receiver Circuit
DS8907N/B+	ETC	获取价格	AM/FM Receiver Circuit
DS8908	TI	获取价格	DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer
DS8908B	NSC	获取价格	DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer

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