DS8907N

更新时间： 2024-09-13 22:22:31

品牌	Logo	应用领域
美国国家半导体 - NSC		信号电路锁相环或频率合成电路光电二极管
页数	文件大小	规格书
8页	166K
描述
Phase-Locked Loop Frequency Synthesizer

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DS8907N 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.92
Is Samacsys：	N	其他特性：	ALSO REQUIRES 4.5V TO 6V SUPPLY
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e0	长度：	26.0731 mm
功能数量：	1	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大供电电流 (Isup)：	160 mA
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

DS8907N 数据手册

July 1986

DS8907 AM/FM Digital

Phase-Locked Loop Frequency Synthesizer

General Description

ble divider divides by (N 1), N being the number loaded

into the shift register (bits 1–13 after address). It is clocked

The DS8907 is a PLL synthesizer designed specifically for

use in AM/FM radios. It contains the reference oscillator, a

phase comparator, a charge pump, a 120 MHz ECL/I L

by the AM input via an ECL -/8 prescaler, or through a

dual modulus programmable divider, and an 18-bit shift reg-

ister/latch for serial data entry. The device is designed to

operate with a serial data controller generating the neces-

sary division codes for each frequency, and logic state infor-

mation for radio function inputs/outputs.

$*/64 prescaler from the FM input. The AM input will work

at frequencies up to 15 MHz, while the FM input works up to

120 MHz. The AM band is tuned with a frequency resolution

of 10 kHz and the FM band is tuned with a resolution of

25 kHz. The buffered AM and FM inputs are self biased and

can be driven directly by the VCO through a capacitor. The

ECL phase comparator produces very accurate resolution

of the phase difference between the input signal and the

reference oscillator. The high speed charge pump consists

The Colpitts reference oscillator for the PLL operates at

4 MHz. A chain of dividers is used to generate a 500 kHz

clock signal for the external controller. Additional dividers

generate a 25 kHz reference signal for FM and a 10 kHz

reference signal for AM. One of these reference signals is

selected by the data from the controller for use by the

phase comparator.

of a switchable constant current source ( 0.3 mA) and a

switchable constant current sink ( 0.3 mA). If the VCO fre-

quency is low, the charge pump will source current, and sink

current if the VCO frequency is high. When using an AFC

Data is transferred between the frequency synthesizer and

the controller via a 3 wire bus system. This consists of a

data input line, an enable line, and a clock line. When the

enable line is low, data can be shifted from the controller

into the frequency synthesizer. When the enable line is tran-

sitioned from low to high, data entry is disabled and data

present in the shift register is latched.

the charge pump output may be forced into TRI-STATE by

applying a low level to the charge pump enable input.

A separate V

pin (typically drawing 1.5 mA) powers the

CCM

oscillator and reference chain to provide controller clocking

frequencies when the balance of the PLL is powered down.

Features

From the controller 20-bit data stream, the first 2 bits ad-

dress the device permitting other devices to share the same

bus. Of the remaining 18-bit data word, the next 13 bits are

used for the PLL divide code. The remaining 5 bits are con-

nected via latches to output pins. These 5 bits can be used

to drive radio functions such as gain, mute, FM, AM and

stereo only. These outputs are open collector. Bit 16 is used

internally to select the AM or FM local oscillator input and to

select between the 10 kHz and 25 kHz reference. A high

level at bit 16 indicates FM and a low level indicates AM.

Uses inexpensive 4 MHz reference crystal

capability greater than 120 MHz allows direct syn-

thesis at FM frequencies

FM resolution of 25 kHz allows usage of 10.7 MHz ce-

ramic filter distribution

Serial data entry for simplified control

50 Hz output for ‘‘time-of-day’’ reference driven from

separate low power V

CCM

5-open collector buffered outputs for controlling various

radio functions

The PLL consists of a 13-bit programmable I L divider, an

ECL phase comparator, an ECL dual modulus (p/p 1) pre-

scaler, and a high speed charge pump. The programma-

Separate AM and FM inputs. AM input has 15 mV (typi-

cal) hysteresis

Dual-In-Line Package

Connection Diagram

Order Number DS8907N

See NS Package Number

N20A

TL/F/7511–1

Top View

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/7511

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7 8

中文翻译

下载PDF

与DS8907N相关器件

型号	品牌	获取价格	描述	数据表
DS8907N/A+	ETC	获取价格	AM/FM Receiver Circuit
DS8907N/B+	ETC	获取价格	AM/FM Receiver Circuit
DS8908	TI	获取价格	DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer
DS8908B	NSC	获取价格	DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer
DS8908BN	NSC	获取价格	DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer
DS8908J/A+	ETC	获取价格	AM/FM Receiver Circuit
DS8908N	ETC	获取价格	AM/FM Receiver Circuit
DS8908N/A+	ETC	获取价格	AM/FM Receiver Circuit
DS8908N/B+	ETC	获取价格	AM/FM Receiver Circuit
DS8911	NSC	获取价格	Sound Up-Conversion Frequency Synthesizer

与DS8907N相关文章

SL74HC10N：高性能三输入与非门解析
2024-09-03

80
AIC1781A 电池充电控制器深度解析
2024-09-03

70
Pickering新高压舌簧继电器亮相汽车测试博览会
2024-08-26

100
采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

117

产品中心

服务支持

精选活动

关于我们

帮助中心

DS8907N

DS8907N 技术参数

DS8907N 数据手册

与DS8907N相关器件

与DS8907N相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS8907N

DS8907N 技术参数

DS8907N 数据手册

与DS8907N相关器件

与DS8907N相关文章

您还可以找

您在本页遇到什么问题？