Datasheet > DS3893A_09

DS3893A_09

更新时间： 2024-11-22 06:54:43

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
8页	281K
描述
BTL TURBOTRANSCEIVER™

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中文翻译

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数据手册

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DS3893A_09 数据手册

OBSOLETE

April 20, 2009

DS3893A

BTL TURBOTRANSCEIVER™

General Description

The bus driver is an open collector NPN with a Schottky diode

in series to isolate the transistor output capacitance from the

bus when the driver is in the inactive state. The active output

low voltage is typically 1V. The bus is intended to be operated

with termination resistors (selected to match the bus

impedance) to 2.1V at both ends. Each of the resistors can

be as low as 20Ω.

The TURBOTRANSCEIVER is designed for use in very high

speed bus systems. The bus terminal characteristics of the

TURBOTRANSCEIVER are referred to as “Backplane

Transceiver Logic” (BTL). BTL is a new logic signaling stan-

dard that has been developed to enhance the performance of

backplane buses. BTL compatible transceivers feature low

output capacitance drivers to minimize bus loading, a 1V

nominal signal swing for reduced power consumption and re-

ceivers with precision thresholds for maximum noise immu-

nity. This new standard eliminates the settling time delays,

that severely limit the TTL bus performance, to provide sig-

nificantly higher bus transfer rates.

Features

Fast single ended transceiver (typical driver enable and

receiver propagation delays are 3.5 ns and 5 ns)

■

Backplane Transceiver Logic (BTL) levels (1V logic swing)

■

Less than 5 pF bus-port capacitance

The TURBOTRANSCEIVER is compatible with the require-

ments of the proposed IEEE 896 Futurebus draft standard. It

is similar to the DS3896/97 BTL TRAPEZOIDAL™

Transceivers but the trapezoidal feature has been removed

to improve the propagation delay. A stripline backplane is

therefore required to reduce the crosstalk induced by the

faster rise and fall times. This device can drive a 10Ω load

with a typical propagation delay of 3.5 ns for the driver and

5 ns for the receiver.

Drives densely loaded backplanes with equivalent load

impedances down to 10Ω

4 transceivers in 20 pin PCC package

■

Specially designed for stripline backplanes

Separate bus ground returns for each driver to minimize

ground noise

High impedance, MOS and TTL compatible inputs

TRI-STATE^®control for receiver outputs

■

When multiple devices are used to drive a parallel bus, the

driver enables can be tied together and used as a common

control line to get on and off the bus. The driver enable delay

is designed to be the same as the driver propagation delay in

order to provide maximum speed in this configuration. The

low input current on the enable pin eases the drive required

for the common control line.

Built-in bandgap reference provides accurate receiver

threshold

Glitch free power up/down protection on all outputs

■

Oxide isolated bipolar technology

Connection and Logic Diagram

869801

Order Number DS3893AV

See NS Package Number V20A

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

8698

www.national.com

8698 Version 7 Revision 5 Print Date/Time: 2009/04/20 13:55:11

12 3 4 5 6 7 8

中文翻译

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与DS3893A_09相关器件

型号	品牌	获取价格	描述	数据表
DS3893AV	NSC	获取价格	BTL TURBOTRANSCEIVER⑩
DS3893AV/NOPB	TI	获取价格	LINE TRANSCEIVER, PQCC20
DS3893AVX	ETC	获取价格	4-Bit Bus Transceiver
DS3893V	ETC	获取价格	4-Bit Bus Transceiver
DS3894	ZARLINK	获取价格	PRECISION SERVO INTEGRATED CIRCUIT
DS3896	NSC	获取价格	BTL Trapezoidal⑩ Transceivers
DS3896_09	NSC	获取价格	BTL Trapezoidal™ Transceivers
DS3896J	ETC	获取价格	Single 8-Bit Inverting Bus Transceiver
DS3896J/A+	ETC	获取价格	Single 8-Bit Inverting Bus Transceiver
DS3896M	NSC	获取价格	BTL Trapezoidal⑩ Transceivers

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