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DS3893AV PDF预览

DS3893AV

更新时间: 2024-11-21 22:40:39
品牌 Logo 应用领域
美国国家半导体 - NSC 接口集成电路
页数 文件大小 规格书
7页 617K
描述
BTL TURBOTRANSCEIVER⑩

DS3893AV 数据手册

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March 1997  
DS3893A  
BTL TURBOTRANSCEIVER  
General Description  
The bus driver is an open collector NPN with a Schottky  
diode in series to isolate the transistor output capacitance  
from the bus when the driver is in the inactive state. The  
active output low voltage is typically 1V. The bus is intended  
to be operated with termination resistors (selected to match  
the bus impedance) to 2.1V at both ends. Each of the  
resistors can be as low as 20.  
The TURBOTRANSCEIVER is designed for use in very high  
speed bus systems. The bus terminal characteristics of the  
TURBOTRANSCEIVER are referred to as “Backplane  
Transceiver Logic” (BTL). BTL is a new logic signaling stan-  
dard that has been developed to enhance the performance  
of backplane buses. BTL compatible transceivers feature  
low output capacitance drivers to minimize bus loading, a 1V  
nominal signal swing for reduced power consumption and  
receivers with precision thresholds for maximum noise im-  
munity. This new standard eliminates the settling time de-  
lays, that severely limit the TTL bus performance, to provide  
significantly higher bus transfer rates.  
Features  
n Fast single ended transceiver (typical driver enable and  
receiver propagation delays are 3.5 ns and 5 ns)  
n Backplane Transceiver Logic (BTL) levels (1V logic  
swing)  
n Less than 5 pF bus-port capacitance  
n Drives densely loaded backplanes with equivalent load  
impedances down to 10Ω  
n 4 transceivers in 20 pin PCC package  
n Specially designed for stripline backplanes  
n Separate bus ground returns for each driver to minimize  
ground noise  
The TURBOTRANSCEIVER is compatible with the require-  
ments of the proposed IEEE 896 Futurebus draft standard. It  
is similar to the DS3896/97 BTL TRAPEZOIDAL Trans-  
ceivers but the trapezoidal feature has been removed to  
improve the propagation delay. A stripline backplane is there-  
fore required to reduce the crosstalk induced by the faster  
rise and fall times. This device can drive a 10load with a  
typical propagation delay of 3.5 ns for the driver and 5 ns for  
the receiver.  
n High impedance, MOS and TTL compatible inputs  
n TRI-STATE control for receiver outputs  
When multiple devices are used to drive a parallel bus, the  
driver enables can be tied together and used as a common  
control line to get on and off the bus. The driver enable delay  
is designed to be the same as the driver propagation delay in  
order to provide maximum speed in this configuration. The  
low input current on the enable pin eases the drive required  
for the common control line.  
n Built-in bandgap reference provides accurate receiver  
threshold  
n Glitch free power up/down protection on all outputs  
n Oxide isolated bipolar technology  
Connection and Logic Diagram  
00869801  
Order Number DS3893AV  
See NS Package Number V20A  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
TRAPEZOIDAL and TURBOTRANSCEIVER are trademarks of National Semiconductor Corp.  
© 2004 National Semiconductor Corporation  
DS008698  
www.national.com  

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