DS36C280
www.ti.com
SNLS097C –JULY 2000–REVISED FEBRUARY 2013
DS36C280 Slew Rate Controlled CMOS EIA-RS-485 Transceiver
Check for Samples: DS36C280
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FEATURES
DESCRIPTION
The DS36C280 is a low power differential bus/line
transceiver designed to meet the requirements of RS-
485 Standard for multipoint data transmission. In
addition, it is compatible with TIA/EIA-422-B.
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100% RS-485 Compliant
Guaranteed RS-485 Device Interoperation
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Low Power CMOS Design: ICC 500 μA max
Adjustable Slew Rate Control
The slew rate control feature allows the user to set
the driver rise and fall times by using an external
resistor. Controlled edge rates can reduce switching
EMI.
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Minimizes EMI Effects
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Built-In Power Up/Down Glitch-Free Circuitry
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Permits Live Transceiver
Insertion/Displacement
The CMOS design offers significant power savings
over its bipolar and ALS counterparts without
sacrificing ruggedness against ESD damage. The
device is ideal for use in battery powered or power
conscious applications. ICC is specified at 500 μA
maximum.
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SOIC Packages
Industrial Temperature Range: −40°C to
+85°C
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On-board Thermal Shutdown Circuitry
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Prevents Damage to the Device in the Event
of Excessive Power Dissipation
The driver and receiver outputs feature TRI-STATE
capability. The driver outputs operate over the entire
common mode range of −7V to +12V. Bus contention
or fault situations are handled by a thermal shutdown
circuit, which forces the driver outputs into the high
impedance state.
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Wide Common Mode Range: −7V to +12V
(1)
Receiver Open Input Fail-safe
¼ unit load (DS36C280): ≥128 nodes
½ unit load (DS36C280T): ≥64 nodes
ESD (human body model): ≥2 kV
The receiver incorporates a fail safe circuit which
guarantees a high output state when the inputs are
(1)
left open
.
(1) Non-terminated, Open Inputs only
Connection and Logic Diagram
Figure 1. See Package Number D (R-PDSO-G8)
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PRODUCTION DATA information is current as of publication date.
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