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DS34S108

更新时间： 2024-11-23 06:54:39
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美信 - MAXIM /
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13页 1302K
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Single/Dual/Quad/Octal TDM-over-Packet Chip

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DS34S108 数据手册

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ABRIDGED DATA SHEET  
Rev: 101708  
DS34S101, DS34S102, DS34S104, DS34S108  
Single/Dual/Quad/Octal TDM-over-Packet Chip  
General Description  
Features  
♦
♦
Transport of E1, T1, E3, T3 or STS-1 TDM or  
CBR Serial Signals Over Packet Networks  
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC  
compliant devices allow up to eight E1, T1 or serial  
streams or one high-speed E3, T3, STS-1 or serial  
stream to be transported transparently over IP, MPLS  
or Ethernet networks. Jitter and wander of recovered  
clocks conform to G.823/G.824, G.8261, and TDM  
specifications. TDM data is transported in up to 64  
individually configurable bundles. All standards-  
based TDM-over-packet mapping methods are  
supported except AAL2. Frame-based serial HDLC  
data flows are also supported. The high level of  
integration available with the DS34S10x devices  
minimizes cost, board space, and time to market.  
Full Support for These Mapping Methods:  
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,  
Unstructured, Structured, Structured with CAS  
♦
♦
♦
Adaptive Clock Recovery, Common Clock,  
External Clock and Loopback Timing Modes  
On-Chip TDM Clock Recovery Machines, One  
Per Port, Independently Configurable  
Clock Recovery Algorithm Handles Network  
PDV, Packet Loss, Constant Delay Changes,  
Frequency Changes and Other Impairments  
♦
♦
64 Independent Bundles/Connections  
Multiprotocol Encapsulation Supports IPv4,  
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet  
Applications  
♦
♦
♦
♦
VLAN Support According to 802.1p and 802.1Q  
10/100 Ethernet MAC Supports MII/RMII/SSMII  
Selectable 32-Bit, 16-Bit or SPI Processor Bus  
TDM Circuit Extension Over PSN  
o
o
o
o
Leased-Line Services Over PSN  
TDM Over GPON/EPON  
TDM Over Cable  
Operates from Only Two Clock Signals, One for  
Clock Recovery and One for Packet Processing  
TDM Over Wireless  
Cellular Backhaul Over PSN  
Multiservice Over Unified PSN  
HDLC-Based Traffic Transport Over PSN  
♦
♦
Glueless SDRAM Buffer Management  
Low-Power 1.8V Core, 3.3V I/O  
See detailed feature list in Section 5 .  
Functional Diagram  
Ordering Information  
PART  
PORTS TEMP RANGE PIN-PACKAGE  
CPU  
Bus  
DS34S101GN *  
DS34S101GN+*  
DS34S102GN*  
DS34S102GN+*  
DS34S104GN  
DS34S104GN+  
DS34S108GN  
DS34S108GN+  
1
1
2
2
4
4
8
8
256 TECSBGA  
256 TECSBGA  
256 TECSBGA  
256 TECSBGA  
256 TECSBGA  
256 TECSBGA  
484 HSBGA  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
DS34S108  
Circuit  
Emulation  
Engine  
10/100  
Ethernet  
xMII  
Interface  
TDM  
Interfaces  
MAC  
Clock  
Adapters  
Buffer  
Manager  
484 HSBGA  
SDRAM  
Interface  
Clock Inputs  
+Denotes lead-free/RoHS-compliant package (explanation).  
*Future product—contact factory for availability.  
________________________________________________________ Maxim Integrated Products  
1
Some revisions of this device may incorporate deviations from published specifications known as errata.  
Multiple revisions of any device may be simultaneously available through various sales channels. For  
information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering  
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
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