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DS34T101GN+* PDF预览

DS34T101GN+*

更新时间： 2024-09-26 02:54:27
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美信 - MAXIM /
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74页 804K
描述
Single/Dual/Quad/Octal TDM-Over-Packet Chip

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DS34T101GN+* 数据手册

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Rev: 072707  
DS34T101/DS34T102/DS34T104/DS34T108  
Single/Dual/Quad/Octal TDM-Over-Packet Chip  
General Description  
Features  
The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC  
draft-compliant DS34T108 allows up to eight T1/E1  
links or frame-based serial HDLC links to be  
transported transparently through a switched IP or  
MPLS packet network. Jitter and wander of  
recovered clocks conform to G.823/G.824, G.8261,  
and TDM specifications. This eliminates the need for  
remote timing sources in cabinets and pedestals.  
♦
♦
Full-Featured T1/E1/J1 LIU/Framer/TDM-Over-  
Packet  
Supports Adaptive Clock Recovery, Common  
Clock (Using RTP), External Clock, and  
Loopback Timing Modes  
♦
♦
♦
Selectable 32-Bit or 16-Bit Processor Bus  
Clock Rate Adapter for T1/E1 Master Clock  
10/100 Ethernet MAC That Supports  
MII/RMII/SSMII  
The Ethernet side of the DS34T108 provides high  
QoS capabilities to its MII/RMII/SSMII port, while the  
WAN side supports full-featured T1/E1 framers and  
LIUs. This takes the solution all the way through  
analog, while preserving options to make use of TDM  
streams at key intermediate points. The high level of  
integration that the DS34T108 brings minimizes cost,  
board space, and time to market.  
♦
♦
♦
Fully Compatible with IEEE 802.3 Standard  
VLAN Support According to 802.1 p&Q  
Multiprotocol Encapsulation Supports IPv4,  
IPv6, UDP, RTP, L2TPv3, MPLS, and Metro  
Ethernet  
♦
End-to-End TDM Synchronization Through  
the IP/MPLS Domain by Eight Independent  
On-Chip TDM Clock Recovery Mechanisms  
Applications  
♦
♦
♦
Single Serial Support for RS-530 and V.35  
Single DS3/E3/STS-1 to Ethernet  
TDM Circuit Extension Over PSN  
o
o
o
o
Leased—Line Services Over PSN  
TDM Over G/E—PON  
TDM Over Cable  
Packet Loss Compensation and Handling of  
Misordered Packets  
TDM Over WiMAX  
♦
♦
♦
♦
64 Independent Bundle/Connections  
Glueless SDRAM Buffer Management  
1.8V Core, 3.3V I/O  
Cellular Backhaul Over PSN  
Multiservice Over Unified PSN  
HDLC—Based Traffic Transport Over PSN  
Complies with IETF PWE3 RFCs and Drafts  
for CESoPSN, SAToP, TDMoIP, and HDLC  
Functional Diagram  
Features continued in Section 7.  
CPU  
Bus  
Ordering Information  
DS34T108  
Octal  
T1/E1/J1  
Transceiver  
Framers  
PIN-  
PACKAGE  
PART  
PORTS TEMP RANGE  
Circuit  
Emulation  
Engine  
10/100  
Ethernet  
xMII  
DS34T108GN  
DS34T108GN+  
DS34T104GN*  
DS34T104GN+*  
DS34T102GN*  
DS34T102GN+*  
DS34T101GN*  
DS34T101GN+*  
8
8
4
4
2
2
1
1
484 HSBGA  
484 HSBGA  
484 TEBGA  
484 TEBGA  
484 TEBGA  
484 TEBGA  
484 TEBGA  
484 TEBGA  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
MAC  
BERT  
& CAS  
Buffer  
Manager  
LIUs  
CLAD  
TDM  
Access  
SDRAM  
Interface  
Clock Inputs  
+Denotes a lead-free package.  
*Future product—Contact factory for availability.  
Maxim Integrated Products 1  
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple  
revisions of any device may be simultaneously available through various sales channels. For information about  
device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim  
Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
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