DS34S132

更新时间： 2024-11-19 06:54:43

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
18页	505K
描述
32-Port TDM-over-Packet IC

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DS34S132 数据手册

ABRIDGED DATA SHEET

19-4750; Rev 0; 7/09

DS34S132

32-Port TDM-over-Packet IC

General Description

Features



32 Independent TDM Ports with Serial Data,

Clock, and Sync (Data = 64Kbps to 2.048Mbps)

The IETF PWE3 SAToP/CESoPSN/HDLC-compliant

DS34S132 provides the interworking functions that

are required for translating TDM data streams into

and out of TDM-over-Packet (TDMoP) data streams

for L2TPv3/IP, UDP/IP, MPLS (MFA-8), and Metro

Ethernet (MEF-8) networks while meeting the jitter

and wander timing performance that is required by

the public network (ITU G.823, G.824, and G.8261).

Up to 32 TDM ports can be translated into as many

as 256 individually configurable pseudowires (PWs)

for transmission over a 100/1000Mbps Ethernet port.

Each TDM port’s bit rate can vary from 64Kbps to

2.048Mbps to support T1/E1 or slower TDM rates.

PW interworking for TDM-based serial HDLC data is

also supported. A built-in time-slot assignment (TSA)

circuit provides the ability to combine any group of

time slots (TS) from a single TDM port into a single

PW. The high level of integration provides the perfect

solution for high-density applications to minimize

cost, board space, and time to market.



One 100/1000Mbps (MII/GMII) Ethernet MAC

256 Total PWs, 32 PW per TDM Port, with Any

Combination of TDMoP and/or HDLC PWs



PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or

IPv6), Metro Ethernet (MEF-8), or MPLS (MFA-8)



0, 1, or 2 VLAN Tags (IEEE 802.1Q)

Synchronous or Asynchronous TDM Port

Timing

One Clock Recovery Engine per TDM Port with

One Assignable as a Global Reference

Supported Clock Recovery Techniques

Adaptive Clock Recovery

Differential Clock Recovery

Absolute and Differential Timestamps

Independent Receive and Transmit Interfaces

Two Clock Inputs for Direct Transmit Timing



For Structured T1/E1, Each TDM Port Includes

DS0 TSA Block for any Time Slot to Any PW

32 HDLC/CES Engines (256 Total)

Applications

With or Without CAS Signaling

TDM Circuit Emulation Over PSN

TDM Leased-Line Services Over PSN

TDM Over BPON/GPON/EPON

TDM Over Cable

TDM Over Wireless

Cellular Backhaul

Multiservice Over Unified PSN

HDLC-Encapsulated Data Over PSN

For Unstructured, each TDM Port Includes

One HDLC/SAT Engine (32 Total)

Any data rate from 64Kbps to 2.048Mbps



32-Bit or 16-Bit CPU Processor Bus

CPU-Based OAM and Signaling

UDP-specific

Inband VCCV

MEF OAM

“Special” Ethernet Type

ARP

NDP/IPv6

Broadcast DA

Functional Diagram



DDR SDRAM Interface

Low-Power 1.8V Core, 3.3V I/O, 2.5V SDRAM

Ordering Information

PORTS TEMP RANGE PIN-PACKAGE

PART

DS34S132 GN

DS34S132 GN+

676 BGA

-40C to +85C

+Denotes a lead(Pb)-free/RoHS-compliant package.

Maxim Integrated Products

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about device

errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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与DS34S132相关器件

型号	品牌	获取价格	描述	数据表
DS34S132GN	MAXIM	获取价格	32-Port TDM-over-Packet IC
DS34S132GN+	MAXIM	获取价格	32-Port TDM-over-Packet IC
DS34S132GNA2+	MAXIM	获取价格	Framer,
DS34T101	MAXIM	获取价格	Single/Dual/Quad/Octal TDM-Over-Packet Chip
DS34T101_08	MAXIM	获取价格	Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34T101_09	MAXIM	获取价格	Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34T101GN	MAXIM	获取价格	Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34T101GN*	MAXIM	获取价格	Single/Dual/Quad/Octal TDM-Over-Packet Chip
DS34T101GN+	MAXIM	获取价格	Single/Dual/Quad/Octal TDM-Over-Packet Chip
DS34T101GN+*	MAXIM	获取价格	Single/Dual/Quad/Octal TDM-Over-Packet Chip

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