DS3181/DS3182/DS3183/DS3184
Single/Dual/Triple/Quad
ATM/Packet PHYs with Built-In LIU
www.maxim-ic.com
GENERAL DESCRIPTION
FUNCTIONAL DIAGRAM
The DS3181, DS3182, DS3183, and DS3184
(DS318x)
integrate ATM
cell/HDLC
packet
processor(s) with a DS3/E3 framer(s) and LIU(s) to
map/demap ATM cells or packets into as many as
four DS3/E3 physical copper lines with DS3-framed,
E3-framed, or clear-channel data streams on per-port
basis.
POS-PHY
CELL/
PACKET
DS3/E3
FRAMER/
DS3/E3/STS-1
PORTS
OR
PROCESSOR
FORMATTER
APPLICATIONS
UTOPIA
Access Concentrators Multiservice Access
DS318x
Platform (MSAP)
SONET/SDH ADM
SONET/SDH Muxes
PBXs
Multiservice Protocol
Platform (MSPP)
Digital Cross Connect ATM and Frame Relay
FEATURES
Equipment
Test Equipment
Routers and Switches PDH Multiplexer/
ꢀ
Single (DS3181), Dual (DS3182), Triple
(DS3183), or Quad (DS3184) with Integrated LIU
ATM/Packet PHYs for DS3, E3, and Clear-
Channel 52Mbps (CC52)
Demultiplexer
Integrated Access
Device (IAD)
ORDERING INFORMATION
ꢀ
Pin Compatible for Ease of Port Density
Migration in the Same PC Board Platform
PART
TEMP RANGE PIN-PACKAGE
ꢀ
ꢀ
Each Port Independently Configurable
400 TE-PBGA (27mm x
DS3181
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
27mm, 1.27mm pitch)
Perform Receive Clock/Data Recovery and
Transmit Waveshaping
400 TE-PBGA (27mm x
DS3181N
DS3182
27mm, 1.27mm pitch)
ꢀ
ꢀ
Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
Interfaces to 75Ω Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3) or 440 Meters or
1443 Feet (E3)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
DS3182N
DS3183
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
ꢀ
ꢀ
Uses 1:2 Transformers on Both Tx and Rx
400 TE-PBGA (27mm x
DS3183N
DS3184
Universal PHYs Map ATM Cells and/or HDLC
27mm, 1.27mm pitch)
Packets into DS3 or E3 Data Streams
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
ꢀ
UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3
Interface with 8-, 16-, or 32-Bit Bus Width
66MHz UTOPIA L3 and POS-PHY L3 Clock
52MHz UTOPIA L2 and POS-PHY L2 Clock
400 TE-PBGA (27mm x
DS3184N
27mm, 1.27mm pitch)
ꢀ
ꢀ
ꢀ
Note: Add the “+” suffix for the lead-free package option.
Ports Independently Configurable for Cell or
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
Packet Traffic in POS-PHY Bus Modes
ꢀ
Direct, PLCP, DSS, and Clear-Channel Cell
Mapping
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 102406