DS3161/DS3162/DS3163/DS3164
Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing........................................... 85
Figure 8-40. 16-Bit Mode Write.................................................................................................................................. 86
Figure 8-41. 16-Bit Mode Read ................................................................................................................................. 86
Figure 8-42. 8-Bit Mode Write.................................................................................................................................... 87
Figure 8-43. 8-Bit Mode Read ................................................................................................................................... 87
Figure 8-44. 16-Bit Mode without Byte Swap ............................................................................................................ 88
Figure 8-45. 16-Bit Mode with Byte Swap ................................................................................................................. 88
Figure 8-46. Clear Status Latched Register on Read................................................................................................ 89
Figure 8-47. Clear Status Latched Register on Write................................................................................................ 89
Figure 8-48. RDY Signal Functional Timing Writes................................................................................................... 90
Figure 8-49. RDY Signal Functional Timing Read..................................................................................................... 90
Figure 10-1. Interrupt Structure ................................................................................................................................. 96
Figure 10-2. Internal TX Clock................................................................................................................................... 99
Figure 10-3. Example I/O Pin Clock Muxing............................................................................................................ 102
Figure 10-4. Reset Sources..................................................................................................................................... 104
Figure 10-5. CLAD Block......................................................................................................................................... 106
Figure 10-6. 8KREF Logic ....................................................................................................................................... 109
Figure 10-7. Performance Monitor Update Logic .................................................................................................... 111
Figure 10-8. Transmit Error Insert Logic.................................................................................................................. 112
Figure 10-9. Loopback Modes................................................................................................................................. 113
Figure 10-10. AIS Signal Flow................................................................................................................................. 115
Figure 10-11. DS3 C-bit or DS3 M23 (with C-bit generation) Frame ...................................................................... 123
Figure 10-12. DS3 PLCP Frame.............................................................................................................................. 124
Figure 10-13. DS3 M23 (with C-bits used as payload) Frame ................................................................................ 125
Figure 10-14. E3 G.751 Frame................................................................................................................................ 125
Figure 10-15. E3 PLCP Frame ................................................................................................................................ 126
Figure 10-16. Example E3 G.751 Internal Fractional Frame................................................................................... 126
Figure 10-17. E3 G.832 Frame................................................................................................................................ 127
Figure 10-18. System Interface Functional Diagram............................................................................................... 128
Figure 10-19. Normal Packet Format in 32-Bit Mode.............................................................................................. 129
Figure 10-20. Normal Packet Format in 16-Bit Mode.............................................................................................. 129
Figure 10-21. Byte Reordered Packet Format in 32-Bit Mode ................................................................................ 129
Figure 10-22. Byte Reordered Packet Format in 16-Bit Mode ................................................................................ 130
Figure 10-23. ATM Cell / HDLC Packet Functional Diagram .................................................................................. 134
Figure 10-24. Receive DSS Scrambler Synchronization State Diagram................................................................. 138
Figure 10-25. Cell Delineation State Diagram......................................................................................................... 139
Figure 10-26. HEC Error Monitoring State Diagram................................................................................................ 140
Figure 10-27. Cell Format for 53-Byte Cell With 32-Bit Data Bus ........................................................................... 140
Figure 10-28. Cell Format for 52-Byte Cell With 32-Bit Data Bus ........................................................................... 141
Figure 10-29. PLCP Framer Functional Diagram.................................................................................................... 146
Figure 10-30. DS3 PLCP Frame Format................................................................................................................. 148
Figure 10-31. DS3 PLCP G1 Byte Format .............................................................................................................. 148
Figure 10-32. E3 PLCP Frame Format.................................................................................................................... 152
Figure 10-33. E3 PLCP G1 Byte Format................................................................................................................. 152
Figure 10-34. Fractional Payload Controller Detailed Block Diagram..................................................................... 156
Figure 10-35. Data Group Format ........................................................................................................................... 158
Figure 10-36. Frame Format.................................................................................................................................... 158
Figure 10-37. Framer Detailed Block Diagram........................................................................................................ 159
Figure 10-38. DS3 Frame Format............................................................................................................................ 161
Figure 10-39. DS3 Subframe Framer State Diagram.............................................................................................. 162
Figure 10-40. DS3 Multiframe Framer State Diagram............................................................................................. 163
Figure 10-41. G.751 E3 Frame Format ................................................................................................................... 170
Figure 10-42. G.832 E3 Frame Format ................................................................................................................... 172
Figure 10-43. MA Byte Format ................................................................................................................................ 173
Figure 10-44. HDLC Controller Block Diagram ....................................................................................................... 178
Figure 10-45. Trail Trace Controller Block Diagram................................................................................................ 182
Figure 10-46. Trail Trace Byte (DT = Trail Trace Data)........................................................................................... 183
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