Datasheet > DS3166N

DS3166N

更新时间： 2024-02-08 21:50:57

品牌	Logo	应用领域
美信 - MAXIM		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
386页	4134K
描述
Transceiver, 1-Func, PBGA676, 27 X 27 MM, 2.28 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-676

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DS3166N 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	27 X 27 MM, 2.28 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-676	针数：	676
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.92	应用程序：	ATM;SDH;SONET
JESD-30 代码：	S-PBGA-B676	JESD-609代码：	e0
长度：	27 mm	功能数量：	1
端子数量：	676	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified	座面最大高度：	2.41 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	27 mm
Base Number Matches：	1

DS3166N 数据手册

DS3166/DS3168/DS31612

6/8/12 ATM/Packet PHYs for

DS3/E3/CC52

www.maxim-ic.com

FEATURES

ꢀ

6 (DS3166), 8 (DS3168), or 12 (DS31612)

ATM/Packet PHYs for DS3, E3, or Clear-Channel

Up to 52Mbps

ꢀ

On-Chip Per-Port BERTs for PRBS and Repetitive

Pattern Generation, Detection, and Analysis

Large Performance-Monitoring Counters for

Accumulation Intervals of at Least 1 Second

High-Speed Flexible Overhead Insertion/

Extraction Ports for DS3, E3, and PLCP Framers

Loopbacks Include Line, Diagnostic, Framer,

Payload, and System Interface

ꢀ

Each Port Independently Configurable

Interfaces to LIUs or SONET/SDH Devices

Universal PHYs Map ATM Cells and/or HDLC

Packets into DS3 or E3 Data Streams

6-, 8-, and 12-Port, Pin-Compatible Devices

UTOPIA L2 or L3 or POS-PHY™ L2 or L3 or

ꢀ

Ports can be Disabled to Reduce Power

SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width at ꢀ Integrated Clock Rate Adapter can Generate the

an Operating Frequency Up to 104MHz

Ports Independently Configurable for Cell or

Packet Traffic in POS-PHY/SPI-3 Bus Modes

Direct, PLCP, DSS, and Clear-Channel Cell

Mapping

Direct and Clear-Channel Packet Mapping

Ports Independently Configurable for DS3, E3 Full

and Subrate, and Arbitrary Framing Protocols Up

to 52Mbps

Programmable (Internal) or External Subrate

DS3/E3 Circuitry

Required 44.736MHz for DS3, 34.368MHz for E3,

and/or 51.84MHz for CC52 from a Single

Reference

Clock Rate Adapter Reference Clock Frequency

can be 44.736, 34.368, 77.76, 51.84, or

19.44MHz

ꢀ

8/16-Bit Generic Microprocessor Interface

Transparent Software Upgrade from Existing

DS3161–DS3164 Single–Quad Port ATM/Packet

PHY Devices

ꢀ

Low-Power 1.8V Core, 3.3V I/O Operation (5V

Tolerant I/O)

ꢀ

DS3/E3/PLCP Alarm Generation and Detection

Built-in HDLC Controllers with 256-Byte FIFOs for

DS3 PMDL, G.751 Sn Bit, and G.832 NR/GC

Bytes, and PLCP NR/GC Bytes

ꢀ

Small 27mm²(1mm pitch) TE-PBGA Packaging

-40°C to +85°C Industrial Temperature Range

IEEE 1149.1 JTAG Test Port

FUNCTIONAL DIAGRAM

ORDERING INFORMATION

CHANNELS

PART

TEMP RANGE PIN-PACKAGE

676 TE-PBGA

DS3166

0°C to +70°C

(27mm²)

676 TE-PBGA

DS3166N

DS3168

-40°C to +85°C

(27mm²)

676 TE-PBGA

0°C to +70°C

POS-PHY

(27mm²)

CELL/

PACKET

DS3/E3

FRAMER/

DS3/E3 LINE

INTERFACE

676 TE-PBGA

UTOPIA

DS3168N

DS31612

DS31612N

-40°C to +85°C

(27mm²)

PROCESSOR

FORMATTER

676 TE-PBGA

DS3166

0°C to +70°C

(27mm²)

DS3168

DS31612

676 TE-PBGA

-40°C to +85°C

(27mm²)

POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

REV: 102105

12 3 4 5 6 7...386

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