Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> DS31406GN+

DS31406GN+

更新时间： 2024-02-17 15:00:29

品牌	Logo	应用领域
美信 - MAXIM		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式时钟
页数	文件大小	规格书
5页	125K
描述
2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DS31406GN+ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA,	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.28	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	长度：	17 mm
功能数量：	1	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.7 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	17 mm	Base Number Matches：	1

DS31406GN+ 数据手册

ABRIDGED DATA SHEET

DS31406

Detailed Features

Input Clock Features



Two input clocks, differential or CMOS/TTL signal format

Input clocks can be any frequency from 2kHz up to 750MHz

Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3

Per-input fractional scaling (i.e. multiplying by ND where N is a 16-bit integer and D is a 32-bit integer and

N < D) to undo 64B/66B and FEC scaling (e.g., 64/66, 238/255, 237/255, 236/255)

Special mode allows locking to 1Hz input clocks

All inputs constantly monitored by programmable activity monitors and frequency monitors

Fast activity monitor can disqualify the selected reference after a few missing clock cycles

Frequency measurement and frequency monitor thresholds with 0.2ppm resolution

Three optional 2/4/8kHz frame-sync inputs



DPLL Features



Very high-resolution DPLL architecture

Sophisticated state machine automatically transitions between free-run, locked, and holdover states

Revertive or nonrevertive reference selection algorithm

Programmable bandwidth from 0.5mHz to 400Hz

Separately configurable acquisition bandwidth and locked bandwidth

Programmable damping factor: 1.2, 2.5, 5, 10, or 20

Multiple phase detectors: phase/frequency and multicycle

Phase/frequency locking (360 capture) or nearest edge phase locking (180 capture)

Multicycle phase detection and locking (up to 8191UI) improves jitter tolerance and lock time

Phase build-out in response to reference switching for true hitless switching

Less than 1 ns output clock phase transient during phase build-out

Output phase adjustment up to 200ns in 6ps steps with respect to selected input reference

High-resolution frequency and phase measurement

Holdover frequency averaging over 1 second, 5.8 minute and 93.2 minute intervals

Fast detection of input clock failure and transition to holdover mode

Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks

Digital Frequency Synthesizer Features



Seven independently programmable DFS engines

Each DFS can synthesize any 2kHz multiple up to 77.76MHz

Per-DFS phase adjust (1/256UI steps)

Approximately 40ps RMS output jitter

Output APLL Features



Simultaneously produce three high-frequency, low-jitter, rates from the same reference clock, e.g.,

622.08MHz for SONET, 255/237*622.08MHz for OTU2, and156.25MHz for 10GE

Standard telecom output frequencies include 622.08MHz, 155.52MHz and 19.44MHz for SONET/SDH and

156.25MHz, 125MHz, and 25MHz for Synchronous Ethernet



Very high-resolution fractional scaling (i.e., noninteger multiplication)

Less than 1ps RMS output jitter

1 2 345

下载PDF

与DS31406GN+相关器件

型号	品牌	描述	获取价格	数据表
DS31407	MAXIM	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter Differential	获取价格
DS31407	MICROCHIP	The DS31407 is a flexible, high-performance timing IC for diverse frequency conversion and	获取价格
DS31407GN+	MAXIM	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter Differential	获取价格
DS31408	MAXIM	8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock	获取价格
DS31408	MICROCHIP	The DS31408 is a flexible, high-performance timing IC for diverse frequency conversion and	获取价格
DS31408_1107	MAXIM	8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock	获取价格

与DS31406GN+相关文章

PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

7
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
2024-05-21

6
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
2024-05-21

9
一文带你了解压敏电阻器在直流电路中的过压保护作用
2024-05-21

5

产品中心

服务支持

精选活动

关于我们

帮助中心

DS31406GN+

DS31406GN+ 技术参数

DS31406GN+ 数据手册

与DS31406GN+相关器件

与DS31406GN+相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS31406GN+

DS31406GN+ 技术参数

DS31406GN+ 数据手册

与DS31406GN+相关器件

与DS31406GN+相关文章

您还可以找

您在本页遇到什么问题？