Datasheet > DS2482S-100/T&R

DS2482S-100/T&R

更新时间： 2024-01-28 01:33:51

品牌	Logo	应用领域
达拉斯 - DALLAS		控制器
页数	文件大小	规格书
21页	255K
描述
Single-Channel 1-Wire Master

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中文翻译

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技术参数
数据手册

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DS2482S-100/T&R 技术参数

生命周期：	Active	包装说明：	SOP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.56
其他特性：	ALSO OPERATES WITH 2.9 TO 3.7 V	接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出电流流向：	SOURCE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	座面最大高度：	1.75 mm
最大供电电压：	5.5 V	最小供电电压：	2.9 V
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	断开时间：	2.2 µs
宽度：	3.9 mm	Base Number Matches：	1

DS2482S-100/T&R 数据手册

DS2482-100: Single-Channel 1-Wire Master

Strong Pullup (SPU)

The SPU bit controls whether the DS2482 will apply a low impedance pullup to V_CCon the 1-Wire line after the last

bit of either a 1-Wire Write Byte command or after a 1-Wire Single Bit command has completed. The strong

pullup feature is commonly used with 1-Wire EEPROM devices when copying scratchpad data to the main memory

or when performing a SHA-1 computation, and with parasitically powered temperature sensors or A-to-D

converters. The respective device data sheets specify the location in the communications protocol after which the

strong pullup should be applied. The SPU bit in the Configuration register of the DS2482 must be set immediately

prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power.

If SPU is 1, the DS2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts,

regardless of the APU bit setting. However, in contrast to setting APU = 1 for active pullup, the low-impedance

pullup does not end after t_APUOTis expired. Instead, as shown in Figure 4, the low-impedance pullup remains active

until either the next 1-Wire communication command is issued (the typical case), the Configuration register is

written to with the SPU bit being 0, or the Device Reset command is issued. The PCTLZ control output is active low

for the entire duration of the low-impedance pullup, enabling an external p-channel MOSFET to supply additional

power to the 1-Wire line. PCTLZ remains inactive (high) at all other time slots that do not use the strong pullup

feature. Additionally, when the pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup does not

change the state of the APU bit in the Configuration register.

Figure 4. Low-Impedance Pullup Timing

Last bit of 1-Wire Write Byte or 1-Wire Single Bit Function

V_cc

Write 1

Edges with

active pull-up

Write 0

Time

t_SLOT

Slot

Pull-up

DS2482 Pull-down

DS2482 Low Impedance Pull-up

1-Wire Speed (1WS)

The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482. All 1-Wire slave

devices support standard speed (1WS = 0), where the transfer of a single bit (t_SLOTin Figure 4) is completed within

65µs. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from

standard to Overdrive speed, a 1-Wire device needs to receive an Overdrive Skip ROM or Overdrive Match ROM

command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device

has received the speed-changing command code. The DS2482 must take part in this speed change to stay

synchronized. This is accomplished by writing to the Configuration register with the 1WS bit being 1 immediately

after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration register

with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482 and any 1-Wire devices on

the active 1-Wire line back to standard speed.

Status Register

The read-only Status register is the general means for the DS2482 to report bit-type data from the 1-Wire side,

1-Wire busy status and its own reset status to the host processor. All 1-Wire communication commands and the

Device Reset command position the read pointer at the Status register for the host processor to read with minimal

protocol overhead. Status information is updated during the execution of certain commands only. Details are given

in the description of the various status bits below.

Status Register Bit Assignment

bit 7

DIR

bit 6

TSB

bit 5

SBR

bit 4

RST

bit 3

bit 2

bit 1

PPD

bit 0

1WB

7 of 21

1...4 5 678 9 10...21

中文翻译

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与DS2482S-100/T&R相关器件

型号	品牌	获取价格	描述	数据表
DS2482S-100+	MAXIM	获取价格	Single-Channel 1-Wire Master
DS2482S-100+TR	MAXIM	获取价格	Single-Channel 1-Wire Master
DS2482S-101+	MAXIM	获取价格	Single-Channel 1-Wire Master with Sleep Mode
DS2482S-101+T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8
DS2482S-101+TR	MAXIM	获取价格	Single-Channel 1-Wire Master with Sleep Mode
DS2482S-800	DALLAS	获取价格	Eight-Channel 1-Wire Master
DS2482S-800/T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO16, 0.150 INCH, SOP-16
DS2482S-800/T&R	DALLAS	获取价格	Eight-Channel 1-Wire Master
DS2482S-800+	MAXIM	获取价格	Eight-Channel 1-Wire Master
DS2482S-800+T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO16, 0.150 INCH, ROHS COMPLIANT, SOP-16

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