Datasheet > DS2482S-100/T&R

DS2482S-100/T&R

更新时间： 2024-02-21 10:17:19

品牌	Logo	应用领域
达拉斯 - DALLAS		控制器
页数	文件大小	规格书
21页	255K
描述
Single-Channel 1-Wire Master

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中文翻译

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技术参数
数据手册

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DS2482S-100/T&R 技术参数

生命周期：	Active	包装说明：	SOP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.56
其他特性：	ALSO OPERATES WITH 2.9 TO 3.7 V	接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出电流流向：	SOURCE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	座面最大高度：	1.75 mm
最大供电电压：	5.5 V	最小供电电压：	2.9 V
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	断开时间：	2.2 µs
宽度：	3.9 mm	Base Number Matches：	1

DS2482S-100/T&R 数据手册

DS2482-100: Single-Channel 1-Wire Master

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Bus Free Time Between a

STOP and START Condition

Capacitive Load for Each Bus

Line

t_BUF

1.3

µs

C_b

(Note 15)

(Note 16)

400

100

µs

Oscillator Warm-Up Time

t_OSCWUP

Note 1:

Note 2:

Operating current with 1-Wire write byte sequence followed by continuous Read of Status register at 400kHz in Overdrive.

With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on

threshold V_IL1may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not

exceed 300pF.

Note 3:

Note 4:

Note 5:

Active pullup guaranteed to turn on between V_IL1MAXand V_IH1MIN.

Active or resistive pullup choice is configurable.

Except for t_F1, all 1-Wire timing specifications and t_APUOTare derived from the same timing circuit. Therefore, if one of these

parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in

the same direction and by the same degree.

Note 6:

These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew

rate is slightly faster.

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

Note 12:

Fall time high-to-low (t_F1) is derived from PD_SRC, referenced from 0.9 × V_CCto 0.1 × V_CC

Presence-pulse masking only applies to standard speed.

All I²C timing values are referred to V_IHminand V_ILmaxlevels.

Applies to SDA, SCL, and AD0, AD1.

I/O pins of the DS2482 do not obstruct the SDA and SCL lines if V_CCis switched off.

The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

Note 13:

Note 14:

The maximum t_HD:_DAThas only to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.

A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t_{SU DAT}

met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + t_{SU DAT}= 1000 + 250 = 1250ns

O250ns must then be

(according to the standard-mode I²C-bus specification) before the SCL line is released.

Note 15:

Note 16:

C_B= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times according to I²C-bus Specification

v2.1 are allowed.

I²C communication should not take place for the max t_OSCWUPtime following a power-on reset.

PIN DESCRIPTION

NAME

V_CC

FUNCTION

Power Supply Input

IO Driver for 1-Wire Line

Ground Reference

I²C Serial Clock Input. Must be tied to V_CCthrough a pullup resistor.

I²C Serial Data Input/Output. Must be tied to V_CCthrough a pullup resistor.

Active-low control output for an external P-channel MOSFET to provide extra power to

the 1-Wire line, e.g., for use with 1-Wire devices that require a higher current temporarily

to operate.

GND

SCL

SDA

PCTLZ

AD1

AD0

I²C Address Inputs. Must be tied to V_CCor GND. These inputs determine the I²C slave

address of the device (see Figure 9).

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与DS2482S-100/T&R相关器件

型号	品牌	获取价格	描述	数据表
DS2482S-100+	MAXIM	获取价格	Single-Channel 1-Wire Master
DS2482S-100+TR	MAXIM	获取价格	Single-Channel 1-Wire Master
DS2482S-101+	MAXIM	获取价格	Single-Channel 1-Wire Master with Sleep Mode
DS2482S-101+T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8
DS2482S-101+TR	MAXIM	获取价格	Single-Channel 1-Wire Master with Sleep Mode
DS2482S-800	DALLAS	获取价格	Eight-Channel 1-Wire Master
DS2482S-800/T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO16, 0.150 INCH, SOP-16
DS2482S-800/T&R	DALLAS	获取价格	Eight-Channel 1-Wire Master
DS2482S-800+	MAXIM	获取价格	Eight-Channel 1-Wire Master
DS2482S-800+T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO16, 0.150 INCH, ROHS COMPLIANT, SOP-16

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