Datasheet > DS2482-800_12

DS2482-800_12

更新时间： 2022-10-27 16:29:57

品牌	Logo	应用领域
美信 - MAXIM		控制器
页数	文件大小	规格书
23页	388K
描述
8-Channel 1-Wire Master

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中文翻译

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数据手册

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DS2482-800_12 数据手册

DS2482-800: 8-Channel 1-Wire Master

Note 1:

Note 2:

Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at

400kHz in Overdrive.

With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the

passive pullup on threshold V_IL1may not be reached in the available time. With Overdrive speed the

capacitive load on the 1-Wire bus must not exceed 300pF.

Note 3:

Note 4:

Note 5:

Note 6:

Active pullup guaranteed to turn on between V_IL1MAXand V_IH1MIN

Active or resistive pullup choice is configurable.

Fall time high to low (t_F1) is derived from PD_SRC,referenced from 0.9 × V_CCto 0.1 × V_CC.

These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced

load, the pulldown slew rate is slightly faster.

Note 7:

Note 8:

Note 9:

Note 10:

All I²C timing values are referred to V_IHminand V_ILmaxlevels.

Applies to SDA, SCL, and AD0, AD1, AD2.

I/O pins of the DS2482 do not obstruct the SDA and SCL lines if V_CCis switched off.

The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V_IHminof the SCL

signal) to bridge the undefined region of the falling edge of SCL.

Note 11:

Note 12:

The maximum t_HD:_DAThas only to be met if the device does not stretch the low period (t_LOW) of the SCL

signal.

A Fast-mode I²C -bus device can be used in a standard-mode I²C -bus system, but the requirement

t_SU:_DAT 250ns must then be met. This is automatically the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must

output the next data bit to the SDA line tr max + t_SU:_DAT= 1000 + 250 = 1250ns (according to the

standard-mode I²C -bus specification) before the SCL line is released.

Note 13:

C_B= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according

to I²C-Bus Specification v2.1 are allowed.

Note 14:

Note 15:

I²C communication should not take place for the max t_OSCWUPtime following a power-on reset.

Except for t_F1, all 1-Wire timing specifications and t_APUOTare derived from the same timing circuit.

Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of

these parameters deviate from their typical value in the same direction and by the same degree.

PIN DESCRIPTION

NAME

FUNCTION

IO3

SCL

SDA

V_CC

IO Driver for 1-Wire Line #3

I²C Serial Clock Input; must be tied to V_CCthrough a pullup resistor.

I²C Serial Data Input/Output; must be tied to V_CCthrough a pullup resistor.

Power Supply Input

Not Connected

AD2

AD1

AD0

IO7

IO6

IO5

IO4

GND

IO0

IO1

IO2

I²C Address Inputs; must be tied to V_CCor GND. These inputs determine the I²C slave

address of the device, see Figure 8.

IO Driver for 1-Wire Line #7

IO Driver for 1-Wire Line #6

IO Driver for 1-Wire Line #5

IO Driver for 1-Wire Line #4

Ground Reference

IO Driver for 1-Wire Line #0

IO Driver for 1-Wire Line #1

IO Driver for 1-Wire Line #2

4 of 23

1 2 345 6 7...23

中文翻译

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与DS2482-800_12相关器件

型号	品牌	获取价格	描述	数据表
DS2482-800_V01	MAXIM	获取价格	8-Channel 1-Wire Master
DS2482S-100	DALLAS	获取价格	Single-Channel 1-Wire Master
DS2482S-100/R	DALLAS	获取价格	Single-Channel 1-Wire Master
DS2482S-100/T	DALLAS	获取价格	Single-Channel 1-Wire Master
DS2482S-100/T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, SOP-8
DS2482S-100/T&R	DALLAS	获取价格	Single-Channel 1-Wire Master
DS2482S-100+	MAXIM	获取价格	Single-Channel 1-Wire Master
DS2482S-100+TR	MAXIM	获取价格	Single-Channel 1-Wire Master
DS2482S-101+	MAXIM	获取价格	Single-Channel 1-Wire Master with Sleep Mode
DS2482S-101+T&R	MAXIM	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8

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