Single-Channel 1-Wire Master with Sleep Mode
Active Pullup (APU)
Device Registers
The APU bit controls whether an active pullup (con-
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The DS2482-101 has three registers that the I C host
trolled slew-rate transistor) or a passive pullup (R
WPU
can read: Configuration, Status, and Read Data. These
registers are addressed by a read pointer. The position
of the read pointer, i.e., the register that the host reads
in a subsequent read access, is defined by the instruc-
tion the DS2482-101 executed last. To enable certain
1-Wire features, the host has read and write access to
the Configuration Register.
resistor) is used to drive a 1-Wire line from low to high.
When APU = 0, active pullup is disabled (resistor
mode). Active pullup should always be selected unless
there is only a single slave on the 1-Wire line. The
active pullup does not apply to the rising edge of a
presence pulse or a recovery after a short on the
1-Wire line.
Configuration Register
The DS2482-101 supports three 1-Wire features that
are enabled or selected through the Configuration
Register. These features are:
The circuit that controls rising edges (Figure 2) oper-
DS482-01
ates as follows: At t , the pulldown (from DS2482-101
1
or 1-Wire slave) ends. From this point on the 1-Wire bus
is pulled high through R
internal to the DS2482-
WPU
101. V
and the capacitive load of the 1-Wire line
CC
• Active Pullup (APU)
• Strong Pullup (SPU)
• 1-Wire Speed (1WS)
determine the slope. In case that active pullup is dis-
abled (APU = 0), the resistive pullup continues, as rep-
resented by the solid line. With active pullup enabled
(APU = 1), and when at t the voltage has reached a
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These features can be selected in any combination.
While APU and 1WS maintain their state, SPU returns to
its inactive state as soon as the strong pullup has
ended.
level between V
and V
, the DS2482-101
IH1(MIN)
IL1(MAX)
actively pulls the 1-Wire line high, applying a controlled
slew rate as represented by the dashed line. The active
pullup continues until t
is expired at t . From that
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APUOT
After a device reset (power-up cycle or initiated by the
Device Reset command), the Configuration Register
reads 00h. When writing to the Configuration Register,
the new data is accepted only if the upper nibble (bits 7
to 4) is the one’s complement of the lower nibble (bits 3
to 0). When read, the upper nibble is always 0h.
time on the resistive pullup continues. See the Strong
Pullup (SPU) section for a way to keep the pullup tran-
sistor conducting beyond t .
3
Configuration Register Bit Assignment
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1WS
SPU
1
APU
1WS
SPU
0
APU
V
CC
APU = 1
APU = 0
V
IH1(MIN)
V
IL1(MAX)
0V
t
1-Wire BUS IS DISCHARGED
APUOT
t
1
t
t
3
2
Figure 2. Rising Edge Pullup
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