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DP8466BV-12 PDF预览

DP8466BV-12

更新时间: 2024-11-01 15:31:03
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟数据传输驱动外围集成电路驱动器
页数 文件大小 规格书
58页 701K
描述
IC 12 Mbps, ST506; SMD; ESDI COMPATIBLE, FIXED DISK CONTROLLER, PQCC68, PLASTIC, CC-68, Secondary Storage Controller

DP8466BV-12 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC68,1.0SQReach Compliance Code:unknown
风险等级:5.92最大时钟频率:12.5 MHz
最大数据传输速率:1.5 MBps驱动器接口标准:ST506; SMD; ESDI
外部数据总线宽度:16主机数据传输速率最大值:6 MBps
主机接口标准:SCSI; IPIJESD-30 代码:S-PQCC-J68
JESD-609代码:e0端子数量:68
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified子类别:Secondary Storage Controllers
最大压摆率:30 mA最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
uPs/uCs/外围集成电路类型:SECONDARY STORAGE CONTROLLER, FIXED DISKBase Number Matches:1

DP8466BV-12 数据手册

 浏览型号DP8466BV-12的Datasheet PDF文件第2页浏览型号DP8466BV-12的Datasheet PDF文件第3页浏览型号DP8466BV-12的Datasheet PDF文件第4页浏览型号DP8466BV-12的Datasheet PDF文件第5页浏览型号DP8466BV-12的Datasheet PDF文件第6页浏览型号DP8466BV-12的Datasheet PDF文件第7页 
June 1990  
DP8466B Disk Data Controller  
General Description  
The DP8466B Disk Data Controller (DDC) is an intelligent  
Features  
Y
Easily conforms to any standard drive interface  
Compatible with floppy, hard and optical disk drives  
Compatible with 8, 16 or 32-bit microprocessor systems  
Programmable disk format  
Y
peripheral which interfaces Winchester or Floppy disk drives  
to microprocessor based systems. It transfers data between  
a buffer memory or host system and the serial bit data  
stream with disk rates up to 25M-bits per second. High  
speed system data transfer is possible with full on-chip DMA  
control of buffer or main memory. The 16-bit system I/O  
interface allows use with any popular 8-bit, 16-bit or 32-bit  
microprocessor. Programmable track format enables recon-  
figuration of the DDC for different drive types in a multiple  
drive environment. Using other National DP846X series disk  
data path chips, the DP8466B conforms to ST506, SMD  
and ESDI standard drive interfaces, as well as to intelligent  
standard interfaces such as SCSI (SASI) and IPI.  
Y
Y
Y
Sector lengths up to 64k bytes, with up to 255 sectors  
per track  
Y
Y
Y
Y
Y
Programmable 32 or 48-bit ECC polynomial  
Internal ECC correction in less than a sector time  
Disk data rate to 25M bits per second  
Multiple sector transfer capability  
32 byte internal FIFO data buffer with interleavable  
burst capability  
Y
Y
Y
Y
8 or 16-bit wide data transfers  
Single 32-bit or dual 16-bit DMA channel addresses  
Up to 10M bytes per second DMA transfer rate  
The DP8466B is available in three performance versions  
DP8466BN-12, DP8466BN-20 and DP8466BN-25.  
a
5V supply, 48 pin DIP, microCMOS process  
Part  
Number  
Max Disk  
Data Rate  
Max DMA  
Transfer Rate  
DP8466BN-25  
DP8466BN-20  
DP8466BN-12  
25 Mbit/sec  
20 Mbit/sec  
12 Mbit/sec  
10 Mbyte/sec  
8 Mbyte/sec  
6 Mbyte/sec  
TL/F/5282–1  
FIGURE 1. Typical System Configuration  
Table of Contents  
1.0 INTRODUCTION  
10.0 SYSTEM CONFIGURATIONS  
11.0 ABSOLUTE MAXIMUM RATINGS  
2.0 PIN DESCRIPTION  
3.0 INTERNAL REGISTERS OF THE DDC  
4.0 DDC OPERATION  
12.0 DC ELECTRICAL CHARACTERISTICS  
13.0 AC ELECTRICAL CHARACTERISTICS AND  
TIMING DIAGRAMS  
5.0 FORMAT, READ AND WRITE  
6.0 CRC/ECC  
14.0 AC TEST CONDITIONS  
15.0 MISCELLANEOUS TIMING INFORMATION  
16.0 FUNCTIONAL STATUS  
17.0 HELPFUL HINTS  
7.0 DATA TRANSFERS  
8.0 INTERRUPTS  
9.0 ADDITIONAL FEATURES  
18.0 APPENDIX  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
MULTIBUSTM is a trademark of Intel Corp.  
C
1995 National Semiconductor Corporation  
TL/F/5282  
RRD-B30M115/Printed in U. S. A.  

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