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DP8421V-33 PDF预览

DP8421V-33

更新时间: 2024-01-17 10:04:45
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动器内存控制器
页数 文件大小 规格书
60页 821K
描述
microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

DP8421V-33 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC68,1.0SQReach Compliance Code:unknown
风险等级:5.63地址总线宽度:20
边界扫描:NO最大时钟频率:33.33 MHz
外部数据总线宽度:JESD-30 代码:S-PQCC-J68
JESD-609代码:e0长度:24.2316 mm
低功率模式:YES内存组织:1M X 1
区块数量:4端子数量:68
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Memory Controllers
最大压摆率:150 mA最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:24.2316 mmuPs/uCs/外围集成电路类型:MEMORY CONTROLLER, DRAM
Base Number Matches:1

DP8421V-33 数据手册

 浏览型号DP8421V-33的Datasheet PDF文件第2页浏览型号DP8421V-33的Datasheet PDF文件第3页浏览型号DP8421V-33的Datasheet PDF文件第4页浏览型号DP8421V-33的Datasheet PDF文件第5页浏览型号DP8421V-33的Datasheet PDF文件第6页浏览型号DP8421V-33的Datasheet PDF文件第7页 
May 1992  
DP8420V/21V/22V-33, DP84T22-25 microCMOS  
Programmable 256k/1M/4M Dynamic RAM  
Controller/Drivers  
General Description  
Features  
Y
On chip high precision delay line to guarantee critical  
DRAM access timing parameters  
The DP8420V/21V/22V-33, DP84T22-25 dynamic RAM  
controllers provide a low cost, single chip interface between  
dynamic RAM and all 8-, 16- and 32-bit systems. The  
DP8420V/21V/22V-33, DP84T22-25 generate all the re-  
quired access control signal timing for DRAMs. An on-chip  
refresh request clock is used to automatically refresh the  
DRAM array. Refreshes and accesses are arbitrated on  
chip. If necessary, a WAIT or DTACK output inserts wait  
states into system access cycles, including burst mode ac-  
cesses. RAS low time during refreshes and RAS precharge  
time after refreshes and back to back accesses are guaran-  
teed through the insertion of wait states. Separate on-chip  
precharge counters for each RAS output can be used for  
memory interleaving to avoid delayed back to back access-  
es because of precharge. An additional feature of the  
DP8422V, DP84T22 is two access ports to simplify dual ac-  
cessing. Arbitration among these ports and refresh is done  
on chip. To make board level circuit testing easier the  
Y
Y
microCMOS process for low power  
High capacitance drivers for RAS, CAS, WE and DRAM  
address on chip  
Y
On chip support for nibble, page and static column  
DRAMs  
Y
Y
TRI-STATE outputs (DP84T22 only)  
Byte enable signals on chip allow byte writing in a word  
size up to 32 bits with no external logic  
Selection of controller speeds: 25 MHz and 33 MHz  
On board Port A/Port B (DP8422V, DP84T22 only)/re-  
fresh arbitration logic  
Y
Y
Y
Y
Direct interface to all major microprocessors (applica-  
tion notes available)  
4 RAS and 4 CAS drivers (the RAS and CAS configura-  
tion is programmable)  
DP84T22 incorporates TRI-STATE output buffers.  
É
Largest  
DRAM  
Possible  
Direct Drive  
Memory  
Capacity  
Access  
Ports  
Available  
Ý
Ý
of Pins  
(PLCC)  
of Address  
Outputs  
Control  
DP8420V  
DP8421V  
DP8422V  
DP84T22  
68  
68  
84  
84  
9
256 kbit  
1 Mbit  
4 Mbit  
4 Mbit  
4 Mbytes  
16 Mbytes  
64 Mbytes  
64 Mbytes  
Single Access Port  
10  
11  
11  
Single Access Port  
Dual Access Ports (A and B)  
Dual Access and TRI-STATE  
Block Diagram  
DP8420V/21V/22V, DP74T22 DRAM Controller  
TL/F/11109–1  
FIGURE 1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
Staggered RefreshTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/11109  
RRD-B30M105/Printed in U. S. A.  

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