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DP8400D-2

更新时间： 2024-01-13 03:23:44
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路
页数 文件大小 规格书
36页 852K
描述
84 SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDIP48, HERMETIC SEALED, DIP-48

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中文翻译

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DP8400D-2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP48,.6Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
系列：84JESD-30 代码：R-CDIP-T48
JESD-609代码：e0负载电容（CL）：50 pF
逻辑集成电路类型：ERROR DETECTION AND CORRECTION CIRCUIT位数：16
功能数量：1端子数量：48
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP48,.6
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED最大电源电流（ICC）：300 mA
传播延迟（tpd）：110 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Arithmetic Circuits
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15.24 mm
Base Number Matches：1

DP8400D-2 数据手册

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May 1989  
2 2  
DP8400-2ÐE C Expandable Error Checker/Corrector  
General Description  
The DP8400-2 Expandable Error Checker and Corrector  
2 2  
(E C ) aids system reliability and integrity by detecting er-  
memory check bits or DP8400-2s than the single-error cor-  
rect configurations.  
The DP8400-2 has a separate syndrome I/O bus which can  
be used for error logging or error management. In addition,  
the DP8400-2 can be used in BYTE-WRITE applications (for  
up to 72 data bits) because it has separate byte controls for  
the data buffers. In 16 or 32-bit systems, the DP8400-2 will  
generate and check system byte parity, if required, for integ-  
rity of the data supplied from or to the processor. There are  
three latch controls to enable latching of data in various  
modes and configurations.  
rors in memory data and correcting single or double-bit er-  
2
2
rors. The E C data I/O port sits across the processor-  
memory data bus as shown, and the check bit I/O port con-  
nects to the memory check bits. Error flags are provided,  
and a syndrome I/O port is available. Fabricated using high  
speed Schottky technology in a 48-pin dual-in-line package,  
the DP8400-2 has been designed such that its internal delay  
times are minimal, maintaining maximum memory perform-  
ance.  
Operational Features  
Y
Fast single and double-error detection  
Y
Fast single-error correction  
Y
Double-error correction after catastrophic failure with no  
additional ICs or check bits  
Y
Functionally expandable to 100% double-error correct  
capability  
Y
Functionally expandable to triple-error detect  
Y
Directly expandable to 32 bits using 2 DP8400-2s only  
Y
Directly expandable to 48 bits using 3 DP8400-2s only  
TL/F/6899–1  
Y
Directly expandable to 64 bits using 4 DP8400-2s only  
For a 16-bit word, the DP8400-2 monitors data between the  
processor and memory, with its 16-bit bidirectional data bus  
connected to the memory data bus. The DP8400-2 uses an  
encoding matrix to generate 6 check bits from the 16 bits of  
data. In a WRITE cycle, the data word and the correspond-  
ing check bits are written into memory. When the same lo-  
Y
Expandable to and beyond 64 bits in fast configuration  
with extra ICs  
Y
3 error flags for complete error recording  
Y
3 latch enable inputs for versatile control  
Y
Byte parity generating and checking  
Y
2
2
Separate byte controls for outputting data in BYTE-  
WRITE operation  
cation of memory is subsequently read, the E C generates  
6 new check bits from the memory data and compares them  
with the 6 check bits read from memory to create 6 syn-  
drome bits. If there is a difference (causing some syndrome  
bits to go high), then that memory location contains an error  
and the DP8400-2 indicates the type of error with 3 error  
flags. If the error is a single data-bit error, the DP8400-2 will  
automatically correct it.  
Y
Separate syndrome I/O port accessible for error  
logging and management  
Y
On-chip input and output latches for data bus, check bit  
bus and syndrome bus  
Y
Diagnostic capability for simulating check bits  
Y
Memory check bit bus, syndrome bus, error flags and  
internally generated syndromes available on the data  
bus  
The DP8400-2 is easily expandable to other data configura-  
a 32-bit data bus with 7 check bits, two  
tions. For  
DP8400-2s can be used in cascade with no other ICs. Three  
DP8400-2s can be used for 48 bits, and four DP8400-2s for  
64 data bits, both with 8 check bits. In all these configura-  
tions, single and double-error detection and single-error cor-  
rection are easy to implement.  
2
2
Y
Self-test of E C on the memory card under processor  
control  
2
Full diagnostic check of memory with the E C  
2
Y
Y
Y
Complete memory failure detectable  
Power-on clears data and syndrome input latches  
When the memory is more unreliable, or better system in-  
tegrity is preferred, then in any of these configurations, dou-  
ble-error correction can be performed. One approach re-  
quires a further memory WRITE-READ cycle using comple-  
mented data and check bits from the DP8400-2. If at least  
one of the two errors is a hard error, the DP8400-2 will  
correct both errors. This implementation requires no more  
Timing Features  
16-BIT CONFIGURATION  
WRITE Time: 29 ns from data-in to check bits valid  
DETECT Time: 21 ns from data-in to Any Error (AE) flag set  
CORRECT Time: 44 ns from data-in to correct data out  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/F/6899  
RRD-B30M105/Printed in U. S. A.  
1234567...36

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