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DP8406QV PDF预览

DP8406QV

更新时间: 2024-02-27 11:20:43
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路
页数 文件大小 规格书
14页 225K
描述
IC 84 SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQCC52, PLASTIC, LCC-52, Arithmetic Circuit

DP8406QV 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC52,.8SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
其他特性:BYTE CONTROL系列:84
JESD-30 代码:S-PQCC-J52JESD-609代码:e0
长度:19.1262 mm负载电容(CL):50 pF
逻辑集成电路类型:ERROR DETECTION AND CORRECTION CIRCUIT位数:32
功能数量:1端子数量:52
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC52,.8SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):340 mA传播延迟(tpd):28 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:19.1262 mmBase Number Matches:1

DP8406QV 数据手册

 浏览型号DP8406QV的Datasheet PDF文件第2页浏览型号DP8406QV的Datasheet PDF文件第3页浏览型号DP8406QV的Datasheet PDF文件第4页浏览型号DP8406QV的Datasheet PDF文件第5页浏览型号DP8406QV的Datasheet PDF文件第6页浏览型号DP8406QV的Datasheet PDF文件第7页 
May 1991  
DP8406 (54F/74F632)  
32-Bit Parallel Error Detection and Correction Circuit  
General Description  
The DP8406 device is a 32-bit parallel error detection and  
correction circuit (EDAC) in a 52-pin or 68-pin package. The  
EDAC uses a modified Hamming code to generate a 7-bit  
check word from a 32-bit data word. This check word is  
stored along with the data word during the memory write  
cycle. During the memory read cycle, the 39-bit words from  
memory are processed by the EDAC to determine if errors  
have occurred in memory.  
detected. Otherwise, errors in three or more bits of the  
39-bit word are beyond the capabilities of these devices to  
detect.  
Read-modify-write (byte-control) operations can be per-  
formed by using output latch enable, LEDBO, and the indi-  
vidual OEB through OEB byte control pins.  
0
3
Diagnostics are performed on the EDACs by controls and  
internal paths that allow the user to read the contents of the  
Data Bit and Check Bit input latches. These will determine if  
the failure occurred in memory or in the EDAC.  
Single-bit errors in the 32-bit data word are flagged and cor-  
rected.  
Single-bit errors in the 7-bit check word are flagged, and the  
CPU sends the EDAC through the correction cycle even  
though the 32-bit data word is not in error. The correction  
cycle will simply pass along the original 32-bit data word in  
this case and produce error syndrome bits to pinpoint the  
error-generating location.  
Features  
Y
Detects and corrects single-bit errors  
Y
Detects and flags dual-bit errors  
Y
Built-in diagnostic capability  
Y
Fast write and read cycle processing times  
Dual-bit errors are flagged but not corrected. These errors  
may occur in any two bits of the 39-bit word from memory  
(two errors in the 32-bit data word, two errors in the 7-bit  
check word, or one error in each word). The gross-error  
condition of all LOWs or all HIGHs from memory will be  
Y
Byte-write capability  
Y
Guaranteed 4000V minimum ESD protection  
Y
Fully pin and function compatible with TI’s  
SN74ALS632A thru SN74ALS635 series  
Simplified Functional Block  
TL/F/9579–9  
Device  
DP8406  
DP8406  
Package  
52-Pin  
Byte-Write  
Output  
TRI-STATE  
TRI-STATE  
yes  
yes  
É
É
68-Pin  
FASTÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9579  
RRD-B30M105/Printed in U. S. A.  

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