DP83901AV PDF预览

DP83901AV

更新时间: 2025-07-15 19:17:47
品牌 Logo 应用领域
德州仪器 - TI 控制器
页数 文件大小 规格书
64页 954K
描述
供电电流(mA):110mA;功能:控制器;元器件封装:68-PLCC;

DP83901AV 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ,针数:68
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.8地址总线宽度:16
边界扫描:NO最大时钟频率:20 MHz
数据编码/解码方法:NRZ; BIPH-LEVEL(MANCHESTER)最大数据传输速率:1.25 MBps
外部数据总线宽度:16JESD-30 代码:S-PQCC-J68
长度:25.13 mm低功率模式:NO
串行 I/O 数:2端子数量:68
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
座面最大高度:4.57 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:25.13 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

DP83901AV 数据手册

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Pin Description (Continued)  
Pin No  
BUS INTERFACE PINS (Continued)  
39 PRQ/ADS1 O, Z PORT REQUEST/ADDRESS STROBE 1  
Pin Name  
I/O  
Description  
32-BIT MODE: If LAS is set in the Data Configuration Register, this line is programmed  
as ADS1. It is used to strobe addresses A16A31 into external latches. (A16A31 are the  
fixed addresses stored in RSAR0, RSAR1). ADS1 will remain at TRI-STATE until BACK is  
received.  
#
16-BIT MODE: If LAS is not set in the Data Configuration Register, this line is programmed as  
PRQ and is used for Remote DMA Transfers. The SNIC initiates a single remote DMA read or  
write operation by asserting this pin. In this mode PRQ will be a standard logic output.  
#
Note: This line will power up as TRI-STATE until the Data Configuration Register is programmed.  
40  
BACK  
I
BUS ACKNOWLEDGE: Bus Acknowledge is an active high signal indicating that the CPU has  
granted the bus to the SNIC. If immediate bus access is desired, BREQ should be tied to BACK.  
Tying BACK to V will result in a deadlock.  
CC  
41  
65  
BREQ  
O
I
BUS REQUEST: Bus Request is an active high signal used to request the bus for Ders.  
This signal is automatically generated when the FIFO needs servicing.  
RESET  
RESET: Reset is active low and places the SNIC in a reset immediaely, no pack
transmitted or received by the SNIC until STA bit is set. Affects Comnd egisterrupt  
Mask Register, Data Configuration Register and Transmit Configuratiogister. TSNIC w
execute reset within 10 BSCK cycles and TXC cycles.  
67  
68  
INT  
O
I
INTERRUPT: Indicates that the SNIC requires CPU attention afteception trsmission or  
completion of DMA transfers. The interrupt is cleared by writ(Interrervice  
Register). All interrupts are maskable.  
WACK  
WRITE ACKNOWLEDGE: Issued from system SNIC to ithat dathas been written to  
the external latch. The SNIC will begin a write cyclplace data in lomemory.  
NETWORK INTERFACE PINS  
b
a
42,  
43  
TX  
TX  
O
TRANSMIT OUTPUT: Differential driver ws the eoded data to the transceiver. The  
outputs are source followers which requwn reors.  
46  
TEST  
I
FACTORY TEST INPUT: Used to checal functions. Tied low during normal  
operation.  
a b  
MODE SELECT: When highransmit anare the same voltage in the idle state.  
47  
SEL  
I
a
b
When low, Transmit is psitive with respect to Transmit in the idle state, at the transformer’s  
primary.  
50  
51  
X1  
I
EXTERNAL OSCILLATOR INPUT  
GND/X2  
O
GROD/X2uld noe connected to ground. It is possible to use a crystal  
oscillatosinX2 if certain precautions are taken. Contact National  
Semicondmation.  
56  
SNISEL  
I
RY TEnormal operation tied to V . When low enables the ENDEC  
CC  
be testndently of the SNIC module.  
b
a
60,  
61  
RX  
RX  
PUT: Diffrential receive input pair from the transceiver.  
b
a
62,  
63  
CD  
CD  
NPUT: Differential collision pair input from the transceiver.  
4

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