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DP83902AVLJ/NOPB PDF预览

DP83902AVLJ/NOPB

更新时间： 2024-01-14 08:53:02
品牌 Logo 应用领域
德州仪器 - TI 时钟局域网数据传输外围集成电路
页数 文件大小 规格书
70页 778K
描述
2 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP100, 14 X 20 MM, EIAJ, PLASTIC, QFP-100

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DP83902AVLJ/NOPB 技术参数

是否Rohs认证：符合生命周期：Obsolete
包装说明：QFP, QFP100,.7X.9Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.82
Is Samacsys：N地址总线宽度：16
边界扫描：NO最大时钟频率：20 MHz
数据编码/解码方法：NRZ; BIPH-LEVEL(MANCHESTER)最大数据传输速率：1.25 MBps
外部数据总线宽度：16JESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
低功率模式：NO湿度敏感等级：3
DMA 通道数量：2I/O 线路数量：
串行 I/O 数：2端子数量：100
片上数据RAM宽度：最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.7X.9
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not QualifiedRAM（字数）：0
座面最大高度：3 mm子类别：Serial IO/Communication Controllers
最大压摆率：140 mA最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

DP83902AVLJ/NOPB 数据手册

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PRELIMINARY  
November 1995  
DP83902A ST-NICTM  
Serial Network Interface Controller for Twisted Pair  
General Description  
Features  
Y
Single chip solution for IEEE 802.3, 10BASE-T  
The DP83902A Serial Network Interface Controller for  
Twisted Pair (ST-NIC) is a microCMOS VLSI device de-  
signed for easy implementation of CSMA/CD local area net-  
works. These include Ethernet (10BASE5), Thin Ethernet  
(10BASE2) and Twisted-pair Ethernet (10BASE-T). The  
overall ST-NIC solution provides the Media Access Control  
(MAC) and Encode-Decode (ENDEC) with an AUI interface,  
and 10BASE-T transceiver functions in accordance with the  
IEEE 802.3 standards.  
Y
Integrated controller, ENDEC, and transceiver  
Y
Full AUI interface  
Y
No external precision components required  
Y
3 levels of loopback supported  
Transceiver Module  
Y
Integrates transceiver electronics, including:  
Ð Transmitter and receiver  
Ð Collision detect, heartbeat and jabber timer  
Ð Link integrity test  
The DP83902A’s 10BASE-T transceiver fully complies with  
the IEEE standard. This functional block incorporates the  
receiver, transmitter, collision, heartbeat, loopback, jabber,  
and link integrity blocks as defined in the standard. The  
transceiver when combined with equalization resistors,  
transmit/receive filters, and pulse transformers provides a  
complete physical interface from the DP83902A’s ENDEC  
module and the twisted pair medium.  
Y
Link disable and polarity detection/correction  
Y
Integrated smart receive squelch  
Y
Reduced squelch level for extended distance cable op-  
eration (100-pin QFP version)  
ENDEC Module  
Y
10 Mb/s Manchester encoding/decoding, plus clock re-  
covery  
The integrated ENDEC module allows Manchester encod-  
ing and decoding via a differential transceiver and phase  
lock loop decoder at 10 Mbit/sec. Also included are colli-  
sion detect translator and diagnostic loopback capability.  
The ENDEC module interfaces directly to the transceiver  
module, and also provides a fully IEEE compliant AUI (At-  
tachment Unit Interface) for connection to other media  
Y
Transmitter half or full step mode  
Y
Squelch on receive and collision pairs  
Y
Lock time 5 bits typical  
Y
g
Decodes Manchester data with up to 18 ns jitter  
MAC/Controller Module  
Y
100% DP8390 software/hardware compatible  
transceivers.  
(Continued)  
Y
Dual 16-bit DMA channels  
Y
16-byte internal FIFO  
Y
Efficient buffer management implementation  
Y
Independent system and network clocks  
Y
Supports physical, multicast and broadcast address fil-  
tering  
Y
Network statistics storage  
1.0 System Diagram  
Station or DTE  
TL/F/11157–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
ST-NICTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/11157  
RRD-B30M115/Printed in U. S. A.  
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